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caravel
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55 Commits

Author SHA1 Message Date
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into 
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
 2021-10-16 17:58:36 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the 
management SoC.
 2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog 
and simulates, but fails testbench (not surprising at this stage).
 2021-10-15 21:49:49 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00