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caravel
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10 Commits

Author SHA1 Message Date
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired 
it to the power supply, and checked top-level LVS.
 2021-11-24 16:50:22 -05:00
Tim Edwards 0114df40ae Added additional power routing from the sides of Caravel to the 
user project power ring.  If that is incompatible with user
projects and/or the XOR check, then this commit might need to be
reverted.
 2021-11-23 16:49:23 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
Tim Edwards 515b5a54f2 Updates for LVS. Only LVS issue remaining for caravel is how to get the 
ground domains to extract independently.
 2021-11-22 12:00:55 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that 
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
 2021-11-21 22:58:39 -05:00
Tim Edwards 5262f35610 Modifications done as part of LVS on the caravel top level. 2021-11-21 22:07:16 -05:00
Tim Edwards d87d60cb9b Finished first draft of the caravel power routing (prior to LVS). 2021-11-21 12:41:46 -05:00
Tim Edwards 29dbc77591 More power routing, still a work in progress. 2021-11-20 22:53:18 -05:00
Tim Edwards 6570429234 Continued work on the power routing. Also updated the management 
core wrapper view with the LEF view from caravel_pico.
 2021-11-20 22:04:46 -05:00
Tim Edwards 8f75362f82 Start of power routing. 2021-11-20 18:04:43 -05:00