4 Commits

Author	SHA1	Message	Date
mo-hosni	e076718887	add `/// sta-blackbox` in the modules that will be blackboxed in STA	2023-05-22 05:52:27 -07:00
Anton Blanchard	25e5e27f9d	Fix issues with port definitions ... Caravel fails to build with recent Icarus Verilog versions because some of the port definitions are not valid.	2023-01-05 20:53:17 +11:00
Tim Edwards	e5c90daddd	Implemented a system for setting the GPIO power-on defaults through ... via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.	2021-10-23 17:18:30 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00