riscv
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caravel
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500 Commits

Author SHA1 Message Date
M0stafaRady 0ec7994476 update caravan netlist with correct risc-v and some missing files 2023-08-07 13:32:37 +03:00
M0stafaRady b9ee241db9
fix compilation error at caravan core caught by iverilog 2023-07-25 13:08:35 +03:00
M0stafaRady de15fea0af update toplevel_cocotb to match the latest updates to compile 1 time 2023-07-05 03:41:30 -07:00
M0stafaRady 1d99f81955 fix path to sdf files 2023-06-21 04:26:25 -07:00
M0stafaRady 33218a99ac add top level for cocotb 2023-06-18 04:18:07 -07:00
mo-hosni e2d21e5893 changed `caravel_logo`, `caravel_motto`, `copyright_block` to `caravan_logo`, `caravan_motto`, `copyright_block_a` respectively in `verilog/gl/caravan.v` to match the layout 2023-06-01 13:46:47 -07:00
Jeff DiCorpo f04c58a8c9
Merge pull request #467 from efabless/caravan-mpw9 
Caravan mpw9
 2023-06-01 10:25:33 -07:00
Passant e88f5abf4f ~ update `caravan` mag and openlane config with the `caravan` specific logo, motto, and copyright 2023-06-01 10:10:11 -07:00
Passant 1e46e15161 ~ update `caravan_core` to fix latch-up DRC violation (non MR) 2023-06-01 09:21:00 -07:00
mo-hosni e25997cc3b swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue 2023-05-30 22:33:33 -07:00
mo-hosni 0c78dbb954 Revert "reharden `caravan_core` to reduce the long wirelengths" 
This reverts commit de16ffc6b9.
 2023-05-30 04:35:59 -07:00
mo-hosni de16ffc6b9 reharden `caravan_core` to reduce the long wirelengths 2023-05-30 02:55:16 -07:00
mo-hosni e911784fb7 reharden `caravan_core` to fix LVS and timing issues 2023-05-29 20:07:08 -07:00
mo-hosni aeb0cbc45f reharden `caravan_core` to fix long wires issues 2023-05-29 02:50:45 -07:00
mo-hosni 8de897098d reharden `caravan_core`. Used a lib for the `user_analog_project_wrapper` and fixed DRCs. 2023-05-24 13:53:03 -07:00
mo-hosni fbf53572e1 reharden `housekeeping_alt` 2023-05-24 02:34:43 -07:00
mo-hosni 59cf3da287 add the analog connections in `caravan_core` GL 2023-05-24 00:42:28 -07:00
mo-hosni 3d9243e2cb update `caravan_signal_routing` to get aligned with `caravan_core` 2023-05-23 03:19:33 -07:00
mo-hosni 0c04656e52 add initial views for `caravan` 2023-05-23 03:05:18 -07:00
mo-hosni 26964d5460 add initial physical views for `caravan_core` 2023-05-23 02:16:44 -07:00
mo-hosni 3e7af79115 add `empty_macro_1` 2023-05-22 06:05:08 -07:00
mo-hosni e076718887 add `/// sta-blackbox` in the modules that will be blackboxed in STA 2023-05-22 05:52:27 -07:00
mo-hosni 6b5aa27297 harden `housekeeping_alt` that will be integrated in `caravan_core` 2023-05-22 05:38:41 -07:00
mo-hosni 5339ed15b6 Merge branch 'caravan-mpw9-PnR' of github.com:efabless/caravel into caravan-mpw9-PnR 2023-05-22 02:34:33 -07:00
mo-hosni 4086fb7130 add PnR empty macros to act as placement obstructions 2023-05-22 02:33:57 -07:00
Tim Edwards e2cc50bae3 Copied housekeeping.v to housekeeping_alt.v and extended the 
function for clock routing to include GPIO[30] and GPIO[31], for
use with the caravan chip, which does not have GPIO in locations
14 and 15.  This restores the clock monitoring capability for
caravan.  Eventually, the housekeeping_alt module should become
the only housekeeping module, extending the clock monitoring
function for caravel and allowing the same module to be used for
both caravel and caravan.
 2023-05-19 10:54:18 -04:00
M0stafaRady c5d251bc08 fix some syntax error in caravan 2023-05-17 00:23:41 -07:00
mo-hosni 1b4692cd68 add `verilog/rtl/caravan_core.v` and modified the hierarchy in `verilog/rtl/caravan.v` 2023-05-16 01:18:27 -07:00
Tim Edwards e6169aaf8c Copied files from the original pull request into a new one. Includes 
a few layout updates since the original pull request.  The openframe
design matches the user example in caravel_openframe_project.
 2023-05-08 16:29:24 -04:00
marwaneltoukhy 1236f44456 updated physical verification reports 2023-04-26 17:33:44 +02:00
mo-hosni 907937b20f reharden `caravel_core` using the updated `gpio_defaults_block` 2023-04-20 23:17:38 -07:00
mo-hosni 2b8e7b7e2e reharden `caravel_core` to have `user_id_programming` as a macro 2023-04-20 07:26:58 -07:00
mo-hosni 94a68ad071 update the physical views for `caravel_core` as the previous ones had issues in integration 2023-04-11 07:43:05 -07:00
mo-hosni bd20921b90 reharden `caravel_core` using a newer OpenLane version 2023-04-10 07:14:59 -07:00
mo-hosni 4398773262 reharden `housekeeping` using a newer OpenLane version 2023-04-10 07:13:48 -07:00
mo-hosni 58bc32467d reharden `caravel_core` to fix 1 hold violation at the fast nominal corner. 2023-03-27 04:44:22 -07:00
mo-hosni 05795a470f reharden `caravel_core` 2023-03-26 02:56:12 -07:00
mo-hosni f233f2f708 reharden housekeeping to fix setup violations at the ss-max corner on top-level. 2023-03-13 02:53:49 -07:00
mo-hosni 360b7d4cf2 Reharden `caravel_core`. 2023-03-06 01:24:00 -08:00
mo-hosni bf18ce8985 remove old gate-level netlists. 2023-03-05 01:04:37 -08:00
mo-hosni 3ccbad56dd reharden `caravel_core`. 2023-03-05 00:59:13 -08:00
mo-hosni 725698014a reharden caravel_core after fixing an issue in the RTL of RAM256. 2023-02-28 05:51:06 -08:00
mo-hosni 7fdcd0d930 add missing GLs. 2023-02-27 11:44:04 -08:00
mo-hosni 7c6e956221 reharden caravel using the modified chip_io. 2023-02-27 11:19:33 -08:00
mo-hosni 25e96c9d62 reharden caravel. 2023-02-27 10:39:51 -08:00
mo-hosni 9be48c6a7b implementation of caravel_core. 2023-02-27 10:38:06 -08:00
mo-hosni e560b56db5 reharden spare_logic_block. 2023-02-27 10:37:00 -08:00
mo-hosni 3f29ea49e7 harden mprj_io_buffer. 2023-02-27 10:33:48 -08:00
mo-hosni 5f8e954d95 reharden gpio_logic_high. 2023-02-27 10:29:46 -08:00
mo-hosni 86612d1f08 reharden caravel_clocking. 2023-02-27 10:26:19 -08:00