riscv
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caravel
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106 Commits

Author SHA1 Message Date
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00
Jeff DiCorpo fd885a9b10
Update README.md 2021-10-12 10:28:29 -07:00
Jeff DiCorpo fac8558a37
Update README.md 2021-10-12 09:38:05 -07:00
Jeff DiCorpo 271f978bc8
Update README.md 2021-10-08 08:00:07 -07:00
Jeff DiCorpo 9615b3d0fc
Update README.md 2021-10-07 11:34:30 -07:00
Jeff DiCorpo 1a7a9dcc16
Initial commit 2021-10-07 11:32:23 -07:00