4 Commits

Author	SHA1	Message	Date
Passant	b463e533ec	update caravel rtl/hierarchy: ... + add `mprj_io_buffer` module that is used to guide the router and buffer signals going to the IOs far from the housekeeping + add `caravel_core` rtl that includes all the macros of caravel ~ restructure caravel to `caravel_core` and `chip_io` that includes the padframe ~ update `caravel_clocking` rtl to include `porb` input reset signal from power-on-reset ~ update `gpio_control_block` rtl to buffer `serial_clock` and `serial_load` siganls	2023-02-26 13:43:37 +02:00
Tim Edwards	4cf7aa2983	Changed the synchronized reset to occur on the clock falling edge ... to give more timing margin when reset is released (note to self: shouldn't the ext_reset also be synchronized?).	2021-12-02 14:26:59 -05:00
manarabdelaty	d7ae2e1ac1	[RTL] Move inverter from top level to HK ... - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND	2021-11-16 13:59:17 +02:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00