20e51c8504
Merge pull request #281 from efabless/fix_buffer_cell_for_lvs
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Small change to the signal buffer layouts for LVS.
2022-10-18 17:12:49 +02:00
38902bde45
Merge pull request #292 from efabless/caravel-redesign-digital_pll-decaps
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reharden: digital_pll
2022-10-18 16:35:49 +02:00
4cbf8ca4f6
Merge pull request #291 from efabless/caravel-redesign-clocking-decaps
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reharden: caravel_clocking
2022-10-18 16:35:26 +02:00
68063ddadc
reharden: digital_pll
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~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
2022-10-18 07:07:32 -07:00
fdeb6003f3
Merge branch 'caravel_redesign-digital_pll-no-or' into caravel_redesign
2022-10-18 06:31:00 -07:00
3bd586b50c
reharden: caravel_clocking
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~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
2022-10-18 06:18:30 -07:00
1110ae2fe8
update housekeeping views and openlane configuration
2022-10-18 04:07:27 -07:00
6bed433856
One additional small change to the signal buffer layouts to avoid
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a collision with the lower three right-hand side I/O cells that
was discovered by LVS.
2022-10-17 15:51:43 -04:00
712b784e16
reharden!: digital_pll
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~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
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reharden!: digital_pll
2022-10-17 20:50:01 +02:00
2d147966b9
Update housekeeping views and openlane configuration
2022-10-17 11:37:24 -07:00
e5d9788a43
reharden!: digital_pll
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~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
a8794dff4b
reharden: caravel
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~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
2d28c973ee
added views for caravel with power routing
2022-10-16 19:08:56 -07:00
7ec1eeb010
Merge branch 'caravel_redesign' into caravel_redesign-top-level
2022-10-16 18:39:39 -07:00
69d353f65c
Corrected the verilog and the layout for the caravan version of the
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signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
2409207178
reharden: caravel
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~ add non functional blocks - like caravel_motto
2022-10-16 15:44:27 -07:00
f7e2dc80a6
Made a minor correction to the layout to remove an extra unused
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buffer. This does not affect ongoing top-level routing work, but
is needed for LVS.
2022-10-16 17:57:14 -04:00
704f19b6c7
reharden: caravel
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~ correct placement for spare_logic_block
~ add changes from buffering macro
2022-10-16 12:56:41 -07:00
7ff92e121f
Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level
2022-10-16 11:18:54 -07:00
48ae31205c
Another change to the pin endpoint positions to make sure that they
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have at least 0.28um spacing to the next wire. Not sure that this
is going to solve the router errors, though.
2022-10-16 14:15:12 -04:00
2a3493ed65
Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level
2022-10-16 10:03:54 -07:00
c5e7c67d60
Once again. . . Rewrote the RTL verilog so that only signals
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being buffered pass through the buffer macros. Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
b9a2e697d5
Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level
2022-10-16 08:00:37 -07:00
589f351dcb
Additional modification to move pins up into an uncongested area
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above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections. Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
38e78abfd5
Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level
2022-10-16 07:24:15 -07:00
43b8f9d4fe
Merge branch 'caravel_redesign' into fix_top_buffers_again
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Updating to the most recent caravel_redesign branch version.
2022-10-16 10:05:36 -04:00
aa2dfe9421
Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again
2022-10-16 07:01:55 -07:00
fc0701003c
reharden: caravel
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- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
2022-10-16 06:58:46 -07:00
dcc3c56b83
Some additional corrections to the gpio_signal_buffering cells.
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Corrected one instance where a buffer had incorrectly been replaced
with a decap cell. Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side. Corrected a small
DRC error in a route position at the bottom.
2022-10-16 09:50:20 -04:00
f5a8382395
Merge branch 'caravel_redesign' into fix_top_buffers_again
2022-10-16 05:55:23 -07:00
22dde425ac
add mgmt_protect views and openlane files
2022-10-16 03:14:55 -07:00
507446e719
Merge branch 'caravel_redesign' into fix_top_buffers_again
2022-10-16 02:01:52 -07:00
a77a45babe
Adjustments to the top level buffering cells to do various things
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like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
5d5d019ea1
Revert "add buff_flash_clkrst"
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This reverts commit 2675487322
2022-10-15 08:47:02 -07:00
3db846b119
Fixes issues with the GPIO signal buffering by applying a bounding
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box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
2675487322
add buff_flash_clkrst
2022-10-15 06:38:42 -07:00
316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect
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Update mgmt protect
2022-10-15 11:27:59 +02:00
3361c8787d
Add mgmt_protect views and openlane files
2022-10-15 01:46:22 -07:00
8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers
2022-10-15 00:28:14 +02:00
92e2f5e8a4
Added layout views (.mag, GDS, DEF, and LEF) for the caravan
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variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
2022-10-14 16:06:11 -04:00
0e01725608
add housekeeping views
2022-10-14 09:26:34 -07:00
aadfb57609
reharden: caravel_clocking
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~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
46d44793e2
Added layout for the gpio_signal_buffering module, including GDS,
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LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00
6452f14de0
reimplement caravel with latest blocks updates and a buffer macro
2022-10-13 13:34:47 -07:00
f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst
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Buff flash clkrst
2022-10-13 20:53:18 +02:00
14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views
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Housekeeping final views
2022-10-13 20:47:09 +02:00
e72f819020
Merge pull request #210 from mo-hosni/final_views
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mgmt_protect final views
2022-10-13 20:33:57 +02:00
08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering
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Caravel clocking reharden
2022-10-13 20:13:45 +02:00
c922241c3f
reharden: caravel_clocking
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+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
2022-10-13 10:54:04 -07:00
Marwan Abbas
kareem
mo-hosni
Tim Edwards
Mohamed Shalan
marwaneltoukhy
passant5