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caravel
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272 Commits

Author SHA1 Message Date
Tim Edwards 515b5a54f2 Updates for LVS. Only LVS issue remaining for caravel is how to get the 
ground domains to extract independently.
 2021-11-22 12:00:55 -05:00
Tim Edwards cfeb62dfb4 A number of changes to the caravan netlists, (1) to correct for 
problems that had been fixed recently in caravel, and which cause
the caravan testbench to break, but which were not noticed;  (2)
corrected the count of gpio_control_block modules, which was one
off, with two of them overlapping (not sure how that even passes
simulation, but it did);  (3) fixed a power connection in the
caravel chip_io, which should have caused chip_io to fail LVS,
so apparently LVS was not run on chip_io. . .
 2021-11-22 09:46:21 -05:00
Tim Edwards 1eb023d973 Added isolated substrate markers in mgmt_protect_hv, should fix the 
last of the LVS issues.
 2021-11-21 23:04:45 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that 
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
 2021-11-21 22:58:39 -05:00
Tim Edwards 5262f35610 Modifications done as part of LVS on the caravel top level. 2021-11-21 22:07:16 -05:00
Tim Edwards 60bdc7e6a4 Moved some supply lines over in chip_io_alt for Caravan to make it 
more compatible with the routing that was copied over from Caravel.
 2021-11-21 13:00:44 -05:00
Tim Edwards d87d60cb9b Finished first draft of the caravel power routing (prior to LVS). 2021-11-21 12:41:46 -05:00
Tim Edwards 29dbc77591 More power routing, still a work in progress. 2021-11-20 22:53:18 -05:00
Tim Edwards 6570429234 Continued work on the power routing. Also updated the management 
core wrapper view with the LEF view from caravel_pico.
 2021-11-20 22:04:46 -05:00
Tim Edwards 8f75362f82 Start of power routing. 2021-11-20 18:04:43 -05:00
Tim Edwards b0d3217280 Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag 
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block).  Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there.  Reinstated the copyright, user ID text, open source
logo, and Caravel logo.  Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
 2021-11-20 13:43:49 -05:00
manarabdelaty 1c18c1dae9 [DATA] Update caravel 2021-11-20 17:28:59 +02:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) 2021-11-20 14:43:20 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets 2021-11-19 15:50:36 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty abc8031729 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-18 15:28:25 +02:00
Tim Edwards 488d8fc5bb Fixed another missing line from the management protect block call 
in caravel.v.
 2021-11-18 08:25:13 -05:00
manarabdelaty b71c8bbb36 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-17 21:09:58 +02:00
Tim Edwards 7b82c143b7 Fixed two signals on the mgmt_protect in caravel that got merged 
and scrambled somehow.
 2021-11-17 14:08:47 -05:00
Tim Edwards 96ef5c83fd Corrected the corner pad connections to vssd and vccd, which were 
still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v
and chip_io_alt.v
 2021-11-17 11:44:32 -05:00
manarabdelaty 3cc88cd7fd Add USE POWER/USE GROUND properties to the simple_port lef view 2021-11-17 17:57:23 +02:00
manarabdelaty 979d34b7a9 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-17 16:43:59 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
Tim Edwards 5f1a0029f5 Made the same corrections to caravan as were made to caravel 
(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
 2021-11-17 09:06:42 -05:00
manarabdelaty b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty d7ae2e1ac1 [RTL] Move inverter from top level to HK 
- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND
 2021-11-16 13:59:17 +02:00
Tim Edwards bb1c9fe528 Removed two references for single-macro verilog files that are no 
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
 2021-11-15 17:53:48 -05:00
Tim Edwards 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally 
deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
 2021-11-15 17:13:43 -05:00
Tim Edwards f18a219be4 Modified the set_user_id script so that if it happens to be run on 
a repository where the user_id_programming GDS has been compressed,
it will handle it correctly.
 2021-11-15 16:41:04 -05:00
manarabdelaty 098b4befb2 Add gds view for chip_io 2021-11-15 23:02:01 +02:00
manarabdelaty a5dbe91965 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-15 21:19:43 +02:00
Tim Edwards f28950695d Made adjustments to the padframe routing to move all routes closer 
to the padframe and free up more space for routing in the chip
interior.
 2021-11-15 11:52:08 -05:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 10cf11fbf5 Add gds/lef views for simple_por 2021-11-15 18:08:22 +02:00
manarabdelaty 6203460f57 [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest 
hardened macro components into the caravel and caravan layouts.
 2021-11-15 10:34:52 -05:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 4c9f7630ff Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-15 13:24:42 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00