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caravel
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140 Commits

Author SHA1 Message Date
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations, 
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
 2021-12-03 17:13:53 -05:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
Tim Edwards e0a318d2bf Fixed the GL verilog for caravel and caravan to add the two changes 
just made to the RTL verilog and layout, to separate out hk_cyc_o
and to hook up the housekeeping user_clock input.
 2021-11-30 12:31:07 -05:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards 4c0a2303b1 Modified the GL netlists to match the layout for the GPIO defaults 
blocks;  that is, there are special versions of the block for the
first 6 GPIO pins.  That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
 2021-11-29 20:17:11 -05:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
Tim Edwards fe21089505 Updated caravan with the same addition of four spare logic blocks 
as was made to caravel.
 2021-11-24 17:10:05 -05:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired 
it to the power supply, and checked top-level LVS.
 2021-11-24 16:50:22 -05:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
Tim Edwards 5d3f2a26f4 Corrected the Caravel layout and the Caravel and Caravan GL netlists 
to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side.  Caravel is now LVS clean again (Caravan needs layout
work).
 2021-11-23 11:47:17 -05:00
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL 
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
 2021-11-22 22:35:52 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
Tim Edwards cd68a2aeff Made several corrections to errors found in the netlists: (1) 
Fixed rstb_h, which was being input to low-voltage blocks.  (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be;  the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line.  This should probably be addressed in
housekeeping but would change the current pinout.
 2021-11-22 15:21:06 -05:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) 2021-11-20 14:43:20 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 6203460f57 [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00