caravel

Author	SHA1	Message	Date
Marwan Abbas	7db65f3e32	Added gl netlists for chip_io_alt and gpio_signal_buffering_alt (#327 )	2022-10-21 12:06:20 -07:00
Tim Edwards	c3fc004072	Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.	2021-12-07 10:06:35 -05:00
manarabdelaty	db8cc0580b	[DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view	2021-12-07 14:28:29 +02:00
Tim Edwards	bd6af6dddc	Modified all of the Makefiles to better handle the GL netlist simulations, which is now done through setting an environment variable to point to the location of the management SoC wrapper. Added the missing user project wrappers to the GL directory (copied from the original caravel repository), and also the GL version of chip_io_alt. Modified the caravan_netlists and caravel_netlists files to import the correct list of gate level netlists, which has been reduced by moving "include" statements for components of the management SoC into the management SoC repository (e.g., caravel_pico).	2021-12-03 17:13:53 -05:00