caravel

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	d4b4b7abb8	Fixed one bad error in clock_div which had been done without my knowledge and which went undetected since before MPW-one. Modified the "pll" and "sysctrl" testbenches so that they run and measure something useful. Both exercise the clock monitoring on GPIO outputs functions. The PLL test also runs the digital locked loop (behavioral verilog). The PLL test overlaps sysctrl, but "pll" cannot be run on gate level verilog, whereas "sysctrl" can.	2021-12-06 21:37:51 -05:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00

Author

SHA1

Message

Date

Tim Edwards

d4b4b7abb8

Fixed one bad error in clock_div which had been done without my

knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.

2021-12-06 21:37:51 -05:00

Tim Edwards

332f9ec2e7

Seeding with documentation of pinout and verilog RTL (mostly unchanged

from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).

2021-10-12 16:31:42 -04:00

2 Commits