above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections. Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell. Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side. Corrected a small
DRC error in a route position at the bottom.
Tim Edwards