riscv
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caravel
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4 Commits

Author SHA1 Message Date
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area 
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
 2022-10-16 10:52:53 -04:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things 
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
 2022-10-15 17:35:17 -04:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding 
box to the layout, so that LEF and DEF positions are correct.
 2022-10-15 10:31:35 -04:00
Tim Edwards 92e2f5e8a4 Added layout views (.mag, GDS, DEF, and LEF) for the caravan 
variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
 2022-10-14 16:06:11 -04:00