Commit Graph

138 Commits

Author SHA1 Message Date
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00
M0stafaRady f2ca45358b remove AN.DB folder from git hub 2022-09-30 03:52:34 -07:00
M0stafaRady 7546ce10c7 simple readme 2022-09-30 03:52:34 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39)
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:05:58 -07:00
R. Timothy Edwards ab85f607e9
Corrected the definitions for the pullup and pulldown input modes (#51)
in "defs.h" per the github issue #15 posted by Sylvain Munaut.
2022-04-07 07:46:02 -07:00
Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as
it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared.  This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
2021-12-29 11:24:17 -05:00
Tim Edwards 1526214cc1 Modifications to some of the Makefiles to make the specific RISC-V
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
2021-12-24 13:42:36 -05:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my
knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
2021-12-06 21:37:51 -05:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock"
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 19:38:24 -05:00
Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations,
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 17:13:53 -05:00
Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
2021-12-03 15:06:15 -05:00
manarabdelaty 856539ca59 Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
Tim Edwards e09640425a Added the user-power-down version of hkspi (hkspi_power) to the list
of patterns to run in the Makefile for verilog dv, since that pattern
has been debugged and now runs correctly.
2021-11-03 11:33:13 -04:00
Tim Edwards 1d359690ac Added testbench for checking that the housekeeping SPI is accessible when
the user area is powered down.  Because this requires some changes to the
padframe definition, this testbench currently fails.
2021-11-02 21:58:47 -04:00
Tim Edwards a2aacdb5d2 Removed some commented-out test code from sram_exec.c to make the
code clearer and less cluttered.
2021-10-31 17:06:05 -04:00
Tim Edwards a360b77618 Added a testbench that demonstrates copying a portion of a program in
flash into SRAM and executing it.
2021-10-31 16:58:44 -04:00
Tim Edwards 00e0a5f603 Corrected the two failing testbenches (which needed fixing because
the implementation of the housekeeping module changed the addresses
of the signals being exercised).
2021-10-28 22:20:46 -04:00
Tim Edwards 787f1c3dae Added back wishbone verification tests, specifically those related
to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping).  The two housekeeping tests fail and need to be
debugged.
2021-10-28 17:26:06 -04:00
Tim Edwards 11165bfe3d Added entries in defs.h for the new input enable lines from the
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
2021-10-28 10:13:14 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00
Tim Edwards 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running
into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.
2021-10-21 10:57:20 -04:00
Tim Edwards 000a5266ef Corrected an error in the bitbang testbench (but it does not cause the
testbench to pass).
2021-10-19 23:10:51 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
2021-10-19 17:32:20 -04:00
Tim Edwards e2f6a02688 Added and verified testbenches timer, timer2, uart, and user_pass_thru. 2021-10-18 21:53:09 -04:00
Tim Edwards 0fa2e3bb89 Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem"
does not pass yet and still needs to be debugged).
2021-10-18 20:32:50 -04:00
Tim Edwards 2e57b5da08 Added and debugged two more testbenches, gpio_mgmt and hkspi. 2021-10-18 11:25:26 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
2021-10-16 17:58:36 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog
and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00