problems that had been fixed recently in caravel, and which cause
the caravan testbench to break, but which were not noticed; (2)
corrected the count of gpio_control_block modules, which was one
off, with two of them overlapping (not sure how that even passes
simulation, but it did); (3) fixed a power connection in the
caravel chip_io, which should have caused chip_io to fail LVS,
so apparently LVS was not run on chip_io. . .
deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
around the entire padframe. The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe. This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
Tim Edwards
manarabdelaty