got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping. (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins. The load pin propagates through the chaing like the
other two. Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down. The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master. Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
storage. Not all of these pass simulation checks. Added back the
bit-bang control of the GPIO programming. Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports. There is not yet a testbench for the SRAM read-only
interface.
Tim Edwards
manarabdelaty