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caravel
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3 Commits

Author SHA1 Message Date
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL 
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
 2021-11-22 22:35:52 -05:00
Tim Edwards 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new 
caravan logo layout.  Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
 2021-11-12 16:12:12 -05:00
Tim Edwards 38dbd8d5d9 Added logo graphic for Caravan. 2021-11-09 22:47:31 -05:00