caravel

Author	SHA1	Message	Date
Tim Edwards	4cf7aa2983	Changed the synchronized reset to occur on the clock falling edge to give more timing margin when reset is released (note to self: shouldn't the ext_reset also be synchronized?).	2021-12-02 14:26:59 -05:00
manarabdelaty	d7ae2e1ac1	[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND	2021-11-16 13:59:17 +02:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00

Author

SHA1

Message

Date

Tim Edwards

4cf7aa2983

Changed the synchronized reset to occur on the clock falling edge

to give more timing margin when reset is released (note to self:
shouldn't the ext_reset also be synchronized?).

2021-12-02 14:26:59 -05:00

manarabdelaty

d7ae2e1ac1

[RTL] Move inverter from top level to HK

- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND

2021-11-16 13:59:17 +02:00

Tim Edwards

332f9ec2e7

Seeding with documentation of pinout and verilog RTL (mostly unchanged

from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).

2021-10-12 16:31:42 -04:00