11 Commits

Author	SHA1	Message	Date
D. Mitch Bailey	999d5e2311	Fixed verilog instance name and ports.	2024-09-01 08:23:15 -07:00
David Lindley	d53ed92620	Updated mag files by swapping decap_12 cells with fill_4 and fill_8. Modified the verilog/gl files to match.	2024-08-29 17:22:17 -07:00
Passant	1e46e15161	~ update `caravan_core` to fix latch-up DRC violation (non MR)	2023-06-01 09:21:00 -07:00
mo-hosni	e25997cc3b	swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue	2023-05-30 22:33:33 -07:00
mo-hosni	0c78dbb954	Revert "reharden `caravan_core` to reduce the long wirelengths" ... This reverts commit de16ffc6b9.	2023-05-30 04:35:59 -07:00
mo-hosni	de16ffc6b9	reharden `caravan_core` to reduce the long wirelengths	2023-05-30 02:55:16 -07:00
mo-hosni	e911784fb7	reharden `caravan_core` to fix LVS and timing issues	2023-05-29 20:07:08 -07:00
mo-hosni	aeb0cbc45f	reharden `caravan_core` to fix long wires issues	2023-05-29 02:50:45 -07:00
mo-hosni	8de897098d	reharden `caravan_core`. Used a lib for the `user_analog_project_wrapper` and fixed DRCs.	2023-05-24 13:53:03 -07:00
mo-hosni	59cf3da287	add the analog connections in `caravan_core` GL	2023-05-24 00:42:28 -07:00
mo-hosni	26964d5460	add initial physical views for `caravan_core`	2023-05-23 02:16:44 -07:00