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158 Commits

Author SHA1 Message Date
M0stafaRady 685518477d add folder to store important sessions 2022-10-12 02:03:06 -07:00
M0stafaRady 71829abbc5 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-11 14:00:58 -07:00
M0stafaRady 2a5c7b876b fix some timeout and errors due to cpu became slower and sram interface are deleted 2022-10-11 14:00:49 -07:00
M0stafaRady de6d55f3ee trial for increase SPI clock 2022-10-11 13:44:56 -07:00
M0stafaRady bd40646465 Update caravel to force high at gpio3 at the start of test 2022-10-11 08:30:02 -07:00
M0stafaRady 9cc8ebf28a update verify_cocotb script to include sdf 2022-10-11 07:30:37 -07:00
M0stafaRady 3fe7f3f38b fix tests timeout 2022-10-11 06:04:16 -07:00
M0stafaRady 7fe790649d Add gpio_all_bidir_user test 2022-10-10 15:59:20 -07:00
M0stafaRady 8cca3a5002 Add gpio_all_i_pd_user and gpio_all_i_pu_user 2022-10-10 14:49:24 -07:00
M0stafaRady a572a8ec14 add gpio_all_i_user test 2022-10-10 09:07:32 -07:00
M0stafaRady e2245ad333 enhance gpio_all_i test to include more checkers 2022-10-10 07:42:02 -07:00
M0stafaRady 71d53b9958 added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady 45a885caaa update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT 2022-10-10 04:34:26 -07:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
M0stafaRady 1690c8e068 enhance gpio_all_o test 2022-10-09 06:07:19 -07:00
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00
M0stafaRady d90001eac2 update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
M0stafaRady 2dc29bb207 comment disabling the housekeeping at the begining of each test as it's not needed anymore 2022-10-07 07:02:58 -07:00
M0stafaRady 0f167fc041 update timeout for gpio_all_i_pd and gpio_all_i_pu 2022-10-07 07:02:09 -07:00
M0stafaRady f072e9cb2d Add gpio_all_i_pd 2022-10-07 06:41:21 -07:00
M0stafaRady 6f832589c0 merge caravel_redesign 2022-10-07 06:06:14 -07:00
M0stafaRady e1eba1d534 update gpio_all_i_pu test 2022-10-07 06:04:18 -07:00
M0stafaRady 3eb0b11380 update verify_cocotb.py to remove vcs generate files 2022-10-06 11:18:48 -07:00
M0stafaRady 4f483adb36 update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
M0stafaRady 7e407e1155 Add test hk_disable 2022-10-06 10:12:12 -07:00
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
M0stafaRady fb34d9a541 update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
M0stafaRady a69185dfca update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00
M0stafaRady 1bc78c4eea update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:43:02 -07:00
M0stafaRady 8e72d5e13e Add test uart_loopback 2022-10-06 03:12:44 -07:00
M0stafaRady 6830c79ae8 fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
M0stafaRady a6e7b46128 delete reading from uart register in uart_rx test 2022-10-05 15:07:38 -07:00
M0stafaRady 78613c95cc increase timeout for uart_rx and add uart_ev_pending_write 2022-10-05 15:02:07 -07:00
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
M0stafaRady fca511f306 change docker mount from the home to repo directory and pdk root 2022-10-05 11:10:24 -07:00
M0stafaRady 4610f6b004 Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
Tim Edwards 7276623d3c Corrected the pull-up definition and revised the CSB definition to 
match the corrected defintions (namely, pull-up is configuration
0x0801, and pull-down is configuration 0x0c01).
 2022-10-05 10:02:24 -04:00
M0stafaRady e2b345dcbb Add new test user_pass_thru_rd 2022-10-04 10:55:53 -07:00
M0stafaRady 0bd6c73b7b update verify_cocotb script to merge coverage 2022-10-04 10:47:07 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
M0stafaRady ef9c2e408b fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
M0stafaRady 37244a2514 add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
M0stafaRady e81416bb51 add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
M0stafaRady e945c3b882 fix bug at mgmt_gpio_out by increasing the number of phases 2022-10-03 05:45:55 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00
M0stafaRady 55f6f56921 update verify_cocotb script to run iverilog inside a docker 2022-10-03 01:56:08 -07:00
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
M0stafaRady 9812aedaa1
Update README.md 2022-10-02 15:50:18 +02:00
M0stafaRady f0494ef4b1 update make file to take user_project_wrapper file as input for iverilog 2022-10-02 06:48:29 -07:00
M0stafaRady 927c216a6b Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:38:32 -07:00
M0stafaRady 752d12928b fix iverlog command for the new structure 2022-10-02 06:38:22 -07:00
M0stafaRady d8a4b812e8 update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode 2022-10-02 06:37:12 -07:00
M0stafaRady 00a029fec3
Update README.md 2022-10-02 15:17:21 +02:00
M0stafaRady bf9b363f68
Update README.md 2022-10-02 15:01:15 +02:00
M0stafaRady 32607cc118 delete uart_rx hex 2022-10-02 05:40:44 -07:00
M0stafaRady b045977af0 merge with remote branch 2022-10-02 05:39:23 -07:00
M0stafaRady cb929cb329 Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
M0stafaRady bc9eb2eb31
Update README.md 2022-10-02 14:35:49 +02:00
M0stafaRady 928fc6a2a5
Update README.md 2022-10-02 14:27:42 +02:00
M0stafaRady a0da0fc906
add photo of cocotb structure 2022-10-02 14:10:17 +02:00
M0stafaRady ad053568e7
Create README.md 
add READme in doc file
 2022-10-02 14:09:49 +02:00
M0stafaRady bd712f64d4 rename cocotb.py to verify_cocotb.py 2022-10-02 04:29:48 -07:00
M0stafaRady b5fb97e5f4 rename run.py to cocotb.py 2022-10-02 04:22:44 -07:00
M0stafaRady 9e0be5473d remove hex files from directory 2022-10-02 04:20:32 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 199d5c0f5c fix bug assert csb before reset for the GL sim to work 2022-10-01 12:36:02 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00
M0stafaRady f2ca45358b remove AN.DB folder from git hub 2022-09-30 03:52:34 -07:00
M0stafaRady 7546ce10c7 simple readme 2022-09-30 03:52:34 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39) 
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-08 09:05:58 -07:00
R. Timothy Edwards ab85f607e9
Corrected the definitions for the pullup and pulldown input modes (#51) 
in "defs.h" per the github issue #15 posted by Sylvain Munaut.
 2022-04-07 07:46:02 -07:00
Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as 
it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared.  This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
 2021-12-29 11:24:17 -05:00
Tim Edwards 1526214cc1 Modifications to some of the Makefiles to make the specific RISC-V 
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
 2021-12-24 13:42:36 -05:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my 
knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
 2021-12-06 21:37:51 -05:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock" 
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
 2021-12-06 19:38:24 -05:00
Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations, 
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
 2021-12-03 17:13:53 -05:00
Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for 
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
 2021-12-03 15:06:15 -05:00
manarabdelaty 856539ca59 Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
Tim Edwards e09640425a Added the user-power-down version of hkspi (hkspi_power) to the list 
of patterns to run in the Makefile for verilog dv, since that pattern
has been debugged and now runs correctly.
 2021-11-03 11:33:13 -04:00
Tim Edwards 1d359690ac Added testbench for checking that the housekeeping SPI is accessible when 
the user area is powered down.  Because this requires some changes to the
padframe definition, this testbench currently fails.
 2021-11-02 21:58:47 -04:00
Tim Edwards a2aacdb5d2 Removed some commented-out test code from sram_exec.c to make the 
code clearer and less cluttered.
 2021-10-31 17:06:05 -04:00
Tim Edwards a360b77618 Added a testbench that demonstrates copying a portion of a program in 
flash into SRAM and executing it.
 2021-10-31 16:58:44 -04:00
Tim Edwards 00e0a5f603 Corrected the two failing testbenches (which needed fixing because 
the implementation of the housekeeping module changed the addresses
of the signals being exercised).
 2021-10-28 22:20:46 -04:00
Tim Edwards 787f1c3dae Added back wishbone verification tests, specifically those related 
to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping).  The two housekeeping tests fail and need to be
debugged.
 2021-10-28 17:26:06 -04:00
Tim Edwards 11165bfe3d Added entries in defs.h for the new input enable lines from the 
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
 2021-10-28 10:13:14 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master 
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
 2021-10-21 19:48:24 -04:00
Tim Edwards 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running 
into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.
 2021-10-21 10:57:20 -04:00