Commit Graph

3 Commits

Author SHA1 Message Date
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
2022-10-14 10:51:29 -04:00
Tim Edwards f7ec0cd012 Added buffers to the top level, inside a macro called
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
2022-10-13 13:29:27 -04:00