Commit Graph

134 Commits

Author SHA1 Message Date
manarabdelaty 979d34b7a9 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-17 16:43:59 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
Tim Edwards 5f1a0029f5 Made the same corrections to caravan as were made to caravel
(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
2021-11-17 09:06:42 -05:00
manarabdelaty b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00
manarabdelaty d7ae2e1ac1 [RTL] Move inverter from top level to HK
- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 13:59:17 +02:00
Tim Edwards bb1c9fe528 Removed two references for single-macro verilog files that are no
longer in the PDK but have been folded into larger library files.
With the most recent push to open_pdks to fix an error in the I/O
verilog library, the verilog testbenches once again pass.
2021-11-15 17:53:48 -05:00
Tim Edwards 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally
deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
2021-11-15 17:13:43 -05:00
manarabdelaty 856539ca59 Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
2021-11-06 13:28:26 -04:00
Tim Edwards b8dda9c3b1 (1) Corrected an error from a recent commit where the reset was
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping.  (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins.  The load pin propagates through the chaing like the
other two.  Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
2021-11-03 23:18:36 -04:00
Tim Edwards 3b89cf0efa Corrected the clock signal into the housekeeping module, which was
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down.  The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
2021-11-03 11:30:39 -04:00
Tim Edwards fe1fcbc3a5 Modified the padframe definition to keep the vccd domain continuous
around the entire padframe.  The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe.  This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V.  The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
2021-11-03 10:53:09 -04:00
Tim Edwards 1d359690ac Added testbench for checking that the housekeeping SPI is accessible when
the user area is powered down.  Because this requires some changes to the
padframe definition, this testbench currently fails.
2021-11-02 21:58:47 -04:00
Tim Edwards dd66d1e5ca Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
Tim Edwards 3a57940371 Revised the management protect block to include protections against
an unconnected wishbone bus (unconnected inputs).  Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
2021-10-27 19:36:43 -04:00
Tim Edwards 1e7400c0ac Removed unused definitions from user_defines.v, and added more
explanatory comments.
2021-10-25 16:36:18 -04:00
Tim Edwards 745eee1baa Created an "open frame" version of caravan (and revised the one for
caravel, since it had not been updated since a number of changes to
the caravel top level module).
2021-10-25 16:29:12 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards a7fec91c4c Update to the back-door wishbone access to housekeeping to better
implement the arbitration between SPI and back-door.  The back-door
access flags when it is going to do a read or write, and the SPI
can have an invalid read or fail a write if the SPI is too fast,
but the wishbone access should be valid.  As long as the SPI is
much slower than the core clock (say, 1MHz) then there should be no
contention, which means that contention can always be avoided simply
by slowing the SPI signaling down.
2021-10-24 16:58:47 -04:00
Tim Edwards e6a94449ce Modified the housekeeping SPI to generate a read strobe (or rather
status) so that between rdstb and wrstb, the SPI signals when it is
about to read or write a byte.  The back-door wishbone interface then
stalls the CPU during these periods.  That allows the CPU to continue
running while the SPI is being accessed without data collisions and
without having to stall for the entire time CSB is held low.
Because SCK is asynchronous to the clock, rare collisions are still
possible;  this is not expected to be an issue but might be worth
investigating.
2021-10-23 22:06:24 -04:00
Tim Edwards e5c90daddd Implemented a system for setting the GPIO power-on defaults through
via programming.  The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file.  For the verilog, they are
applied as parameters.  For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
Tim Edwards 3ffe67e652 Changed the SRAM read-only port signal names to match the change
made to the management SoC wrapper definition---this is just
making the nomenclature better (no functional change).
2021-10-22 11:51:07 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00
Tim Edwards 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running
into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.
2021-10-21 10:57:20 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
2021-10-19 17:32:20 -04:00
Tim Edwards 0fa2e3bb89 Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem"
does not pass yet and still needs to be debugged).
2021-10-18 20:32:50 -04:00
Tim Edwards 2e57b5da08 Added and debugged two more testbenches, gpio_mgmt and hkspi. 2021-10-18 11:25:26 -04:00
Tim Edwards 33ca4e11ef Additional corrections, mostly to the housekeeping module. The
top-level simulation now passes the GPIO testbench.
2021-10-17 21:38:40 -04:00
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
2021-10-16 17:58:36 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the
management SoC.
2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog
and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00