+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
- reimplement using a sparecell
- reimplement using newest open_pdks
!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible
!important override abstract lef generated by openlane. openlane
generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition
- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
- to add obstruction before pdn
- to manually insert buffers on some ports
- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn
- misc changes:
* fix openlane makefile to properly detect interactive script
!important still need to run dynamic simulations
!important depends on some updates to openlane
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`
!IMPORTANT - still need to run dynamic simulations
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect
* mgmt_protect updated
* mgmt_protect updated
* remove some via3 to fix power shorts
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
mo-hosni
Marwan Abbas
kareem
Mohamed Hosni
Mohamed Shalan
Kareem Farid
manarabdelaty
Tim Edwards