Commit Graph

104 Commits

Author SHA1 Message Date
Jeff DiCorpo 5d8b579b6c
Merge pull request #49 from efabless/fix_user_id_prog
This commit fixes the issue with the user ID programming block not
2022-03-22 09:36:06 -07:00
Tim Edwards 53abff5bbf This commit fixes the issue with the user ID programming block not
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository.  The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS.  An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
2022-03-22 10:25:25 -04:00
D. Mitch Bailey 35781987e1 Correct gpio_defaults_block_34 instance name in caravel.mag 2022-03-14 15:04:14 -07:00
Tim Edwards 1b3fe4379c Corrected the placement of the isosub layer in the layouts so that
it is exactly overlapping;  this resolves issues with LVS.  Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
2021-12-24 22:22:23 -05:00
manarabdelaty e408d08f93 [DATA] Update gpio_control_block 2021-12-24 22:53:42 +02:00
manarabdelaty 06f05bd296 [DATA] Update mgmt_protect block (lvs clean mag/gds) 2021-12-24 22:19:00 +02:00
manarabdelaty 0225f6b69c [DATA] Update mgmt_core mag/gds to add isosubstrate on the mgmt_protect_hv 2021-12-24 21:51:25 +02:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
Tim Edwards 5f563c3f4f Corrected a statement in the LVS scripts in the mag/ directory that
is Makefile syntax, not bash syntax, and will cause the script to
produce an incorrect LVS result without generating a syntax error.
2021-12-17 22:27:32 -05:00
Tim Edwards b9fdac94ff Corrected a typo in the run_chip_io_alt_lvs.sh script. 2021-12-08 10:06:50 -05:00
Tim Edwards 75f4e49a99 Removed two floating metal2 rectangles from chip_io_alt. 2021-12-08 10:00:57 -05:00
Tim Edwards 8cac89ec74 Changed the user project wrapper and user analog project wrapper
to be abstract views, and modified the LVS scripts accordingly
(they no longer need a special version of the netgen setup
script).  LVS was verified on both caravel and caravan using this
setup.
2021-12-07 22:21:49 -05:00
Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to
match what was done earlier on chip_io.v, and (2) Corrected a
set of four labels in chip_io_alt.mag which had been rotated,
causing an error in LVS.
2021-12-07 17:16:44 -05:00
Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag
and chip_io_alt.mag.
2021-12-07 12:38:18 -05:00
Tim Edwards 79828c00b3 Revised the LVS run scripts to use $PDK_ROOT instead of a hard-
coded path.
2021-12-07 10:32:22 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
2021-12-07 10:06:35 -05:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock"
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 19:38:24 -05:00
manarabdelaty 00c845525a Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-05 19:50:01 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
Tim Edwards 9da6bab4a8 Corrected DRC errors on the non-Manhattan edges of the caravel
and open source logos.  Modified the gpio_defaults_block layout
so that open holes are not created in the metal1 when the vias
are moved by the defaults block configuration script.
2021-12-03 22:21:06 -05:00
Tim Edwards 2691903104 Reworked part of the layouts of both caravel and caravan to move
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL.  This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
2021-12-02 20:45:39 -05:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 85ad4b0e0f Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-02 21:20:59 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
jeffdi 5896df50a8 add files for seal ring 2021-12-01 22:35:39 -08:00
jeffdi cecf6acd85 correcting magicrc file and pdkpath issues 2021-12-01 22:00:31 -08:00
Tim Edwards 0f90c813ed Added a missing route that was not completed in the previous layout
update.  Also changed the defaults block types in the layout so that
they match the gate-level netlist.  This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
2021-11-30 14:38:25 -05:00
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards 84c97b74b2 Corrected the instance names in the layout so that they once again
correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 19:57:33 -05:00
Tim Edwards 960a839456 Removed the read-only GDS references from the mgmt_project_hv.mag
file, which shouldn't be there.
2021-11-29 16:33:51 -05:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
2021-11-27 11:51:30 -05:00
Tim Edwards f67f7b6daf Corrected bad paths on two layouts in mag/ and most of the layouts
in maglef/, all of which were erroneously pointing to paths in
either OpenLane or the user's home directory path.
2021-11-26 20:00:47 -05:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
Tim Edwards fe21089505 Updated caravan with the same addition of four spare logic blocks
as was made to caravel.
2021-11-24 17:10:05 -05:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired
it to the power supply, and checked top-level LVS.
2021-11-24 16:50:22 -05:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
Tim Edwards 9b1a18a15e Finished drawing all of the analog connections to meet cleanly at
the user analog project boundary.
2021-11-23 17:32:52 -05:00
Tim Edwards 0114df40ae Added additional power routing from the sides of Caravel to the
user project power ring.  If that is incompatible with user
projects and/or the XOR check, then this commit might need to be
reverted.
2021-11-23 16:49:23 -05:00
Tim Edwards 0ba8884b00 Added a motto for each chip. Just because. 2021-11-23 15:19:41 -05:00
Tim Edwards 1ff48245e8 Pushing final layout of Caravan, now LVS clean. 2021-11-23 14:06:14 -05:00
Tim Edwards 5d3f2a26f4 Corrected the Caravel layout and the Caravel and Caravan GL netlists
to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side.  Caravel is now LVS clean again (Caravan needs layout
work).
2021-11-23 11:47:17 -05:00
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
2021-11-22 22:35:52 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
Tim Edwards cd68a2aeff Made several corrections to errors found in the netlists: (1)
Fixed rstb_h, which was being input to low-voltage blocks.  (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be;  the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line.  This should probably be addressed in
housekeeping but would change the current pinout.
2021-11-22 15:21:06 -05:00