includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be). This is
functionally the same. Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good). Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change. This
was the only change affecting layout. Also: Revised the "pll"
testbench. This is still ongoing work. Also: Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre. Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
around the entire padframe. The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe. This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
M0stafaRady
Tim Edwards