cells are replaced with the base cells. Routing to pins
is instead done in the "gpio_connects" cells while
improving on the original routing (fewer cross-overs,
multiple vias per contact, wider buses for the analog
signals). Made small adjustments to many of the openframe
wrapper pins to keep them all on a 10nm grid. Moved the
connections previously from the "wrapped" GPIO cell back
from the openframe project border, so that the border can
be clear of all blockages. Added the DEF file of the
wrapper (previously only in the openframe example repo)
to the def/ directory. Note: The modified LVS scripts
depend on the gate-level netlists of the frame, which
have been committed in a prior pull request. This pull
request does not conflict with those files.
This file indicates which verilog files to include for openframe
simulations. Noted that there were references in the file to
GL versions of user_id_programming.v, chip_io_openframe.v, and
caravel_openframe.v. All three of these are already structural
verilog and do not have versions in the gl/ directory.
function for clock routing to include GPIO[30] and GPIO[31], for
use with the caravan chip, which does not have GPIO in locations
14 and 15. This restores the clock monitoring capability for
caravan. Eventually, the housekeeping_alt module should become
the only housekeeping module, extending the clock monitoring
function for caravel and allowing the same module to be used for
both caravel and caravan.
+ add `mprj_io_buffer` module that is used to guide the router and buffer signals going to the IOs far from the housekeeping
+ add `caravel_core` rtl that includes all the macros of caravel
~ restructure caravel to `caravel_core` and `chip_io` that includes the padframe
~ update `caravel_clocking` rtl to include `porb` input reset signal from power-on-reset
~ update `gpio_control_block` rtl to buffer `serial_clock` and `serial_load` siganls
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout. Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.
* Apply automatic changes to Manifest and README.rst
* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Syntax changes that are non-functional from a synthesis perspective.
There are a few errors that are caught by commercial tools and halt
synthesis, which are handled more gracefully by the open source
tool flow. In housekeeping.v: Some wires declared after they are
used. In housekeeping_spi.v: A non-blocking "=" assignment used
where a blocking "<-" assignment was intended.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* cocotb - updates related to enable simulating caraval using iverilog
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Fixed caravan top level power routing and updated views for mag, gds and lef
* caravan(rtl): updates
~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog
* Apply automatic changes to Manifest and README.rst
* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script
* reharden: caravan
+ add non functional blocks
+ add an initial iteration of caravan
* Apply automatic changes to Manifest and README.rst
* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"
This reverts commit 70628f748a.
* fixed caravan top level power routing
* reharden: caravan
based on new power routing
~ guard rtl chip_io power pins in the power macro guard
* Apply automatic changes to Manifest and README.rst
* fixed caravan top level power routing
* rehadren: caravan
+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues
* Apply automatic changes to Manifest and README.rst
* fix power connection in buffering block and regenerate gl
* Apply automatic changes to Manifest and README.rst
* updated views for caravan
* Added extract unique to lvs-gds-cell target. (#313)
* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.
* Apply automatic changes to Manifest and README.rst
* reharden: caravan
~ rtl updated
* fixed caravan mag top level
* updated views for caravan + signoff
* fixed top level cell name
* fix syntax error related to signal initialization place in caravan (#319)
* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Apply automatic changes to Manifest and README.rst
Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched