2 Commits

Author	SHA1	Message	Date
Tim Edwards	43ced83bd8	Correction to the mprj_bitbang testbench to run the test without running ... into issues of contention between the SPI and wishbone interfaces. The testbench now passes, although the contention isn't handled particularly well.	2021-10-21 10:57:20 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00