Commit Graph

26 Commits

Author SHA1 Message Date
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
Tim Edwards 84c97b74b2 Corrected the instance names in the layout so that they once again
correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 19:57:33 -05:00
Tim Edwards 4dac106297 This (late and invasive) change modifies the housekeeping block to
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i.  This
change makes it compatible with the LiteX implementation of the
wishbone bus.
2021-11-29 14:23:30 -05:00
Tim Edwards 543fee18e3 Revised the spare logic block to make sure that all inputs are
reachable from pins on the boundary once it's synthesized.
2021-11-24 09:34:52 -05:00
Tim Edwards 2b156997cb Added a new module with "spare logic" for metal mask fixes. 2021-11-24 09:23:22 -05:00
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
2021-11-22 22:35:52 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
Tim Edwards 1e14d3a4c5 Corrected the rstb_l signal in both caravan and caravel, and corrected
the clock_core signal in caravan.
2021-11-22 13:25:35 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
2021-11-21 22:58:39 -05:00
Tim Edwards 488d8fc5bb Fixed another missing line from the management protect block call
in caravel.v.
2021-11-18 08:25:13 -05:00
Tim Edwards 7b82c143b7 Fixed two signals on the mgmt_protect in caravel that got merged
and scrambled somehow.
2021-11-17 14:08:47 -05:00
manarabdelaty b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00
manarabdelaty d7ae2e1ac1 [RTL] Move inverter from top level to HK
- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 13:59:17 +02:00
Tim Edwards b8dda9c3b1 (1) Corrected an error from a recent commit where the reset was
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping.  (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins.  The load pin propagates through the chaing like the
other two.  Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
2021-11-03 23:18:36 -04:00
Tim Edwards 3b89cf0efa Corrected the clock signal into the housekeeping module, which was
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down.  The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
2021-11-03 11:30:39 -04:00
Tim Edwards dd66d1e5ca Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
Tim Edwards 3a57940371 Revised the management protect block to include protections against
an unconnected wishbone bus (unconnected inputs).  Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
2021-10-27 19:36:43 -04:00
Tim Edwards e5c90daddd Implemented a system for setting the GPIO power-on defaults through
via programming.  The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file.  For the verilog, they are
applied as parameters.  For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
Tim Edwards 3ffe67e652 Changed the SRAM read-only port signal names to match the change
made to the management SoC wrapper definition---this is just
making the nomenclature better (no functional change).
2021-10-22 11:51:07 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
Tim Edwards 33ca4e11ef Additional corrections, mostly to the housekeeping module. The
top-level simulation now passes the GPIO testbench.
2021-10-17 21:38:40 -04:00
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the
management SoC.
2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog
and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00