* Fixed caravan top level power routing and updated views for mag, gds and lef
* caravan(rtl): updates
~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog
* Apply automatic changes to Manifest and README.rst
* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script
* reharden: caravan
+ add non functional blocks
+ add an initial iteration of caravan
* Apply automatic changes to Manifest and README.rst
* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"
This reverts commit 70628f748a.
* fixed caravan top level power routing
* reharden: caravan
based on new power routing
~ guard rtl chip_io power pins in the power macro guard
* Apply automatic changes to Manifest and README.rst
* fixed caravan top level power routing
* rehadren: caravan
+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues
* Apply automatic changes to Manifest and README.rst
* fix power connection in buffering block and regenerate gl
* Apply automatic changes to Manifest and README.rst
* updated views for caravan
* Added extract unique to lvs-gds-cell target. (#313)
* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.
* Apply automatic changes to Manifest and README.rst
* reharden: caravan
~ rtl updated
* fixed caravan mag top level
* updated views for caravan + signoff
* fixed top level cell name
* fix syntax error related to signal initialization place in caravan (#319)
* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Apply automatic changes to Manifest and README.rst
Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
* added views for each step of generating final caravel.gds
* generated the right caravel and caravel-eco gds
* renamed caravel_signoff and removed caravel-non-eco
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
* reharden: caravel
~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing
* update pdn for `caravel_clocking` & `digital_pll`
* added script to update and generate the power routing views
* ~ run update_power_routing_views from the caravel root with prboundary
* fix output message
* added power routing lef, mag and gds
* fix update_power_routing_views saving wrong cell name
* reharden: caravel
~ incorperate pdn changes
~ re-extract spefs
* fix caravel_power_routing views
* fix abs path in maglef views
* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect
* generate a new chip_io gds
* regenerate gpio_control_block due to mag and gds not in sync
* reharden: caravel
~ change config to pass clean routing
~ use updated views of macros
* lvs clean views
* add caravel top-level generated sdf for all corners
* fix absolute path for mgmt_core_wrapper
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
being buffered pass through the buffer macros. Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections. Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell. Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side. Corrected a small
DRC error in a route position at the bottom.
based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks
+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
which had not been correctly annotated for ports and so were
marked only as plain labels, causing issues when using the cell
as a macro inside mgmt_protect.
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo
!important same work arounds as before
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
xschem-generated schematic netlist.
NOTE: None of these modifications change the function of any circuit. The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled. It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.
* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).
* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect
* mgmt_protect updated
* mgmt_protect updated
* remove some via3 to fix power shorts
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository. The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS. An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
Jeff DiCorpo
Marwan Abbas
marwaneltoukhy
kareem
mo-hosni
Tim Edwards
Mohamed Shalan
Passant
passant5
Mohamed Hosni
Kareem Farid
manarabdelaty
jeffdi