4 Commits

Author	SHA1	Message	Date
Tim Edwards	fe21089505	Updated caravan with the same addition of four spare logic blocks ... as was made to caravel.	2021-11-24 17:10:05 -05:00
Tim Edwards	5d3f2a26f4	Corrected the Caravel layout and the Caravel and Caravan GL netlists ... to resolve the problem with the typo that caused the propagated GPIO serial load, reset, and clock signals to get scrambled on the user2 side. Caravel is now LVS clean again (Caravan needs layout work).	2021-11-23 11:47:17 -05:00
Tim Edwards	08a2c90940	Made updates to correct LVS errors in caravan. Found one major error in the RTL ... verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.	2021-11-22 22:35:52 -05:00
manarabdelaty	aeffe4756a	[DATA] Add caravan layout	2021-11-22 23:10:25 +02:00