riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

add openlane configs for gpio_signal_buffering blocks (#305) 

* add openlane configs for gpio_signal_buffering blocks
to generate verilog gl

* change copyright date

* remove extra empty line
This commit is contained in:
Kareem Farid 2022-10-19 21:30:30 +02:00 committed by GitHub
parent 23b2045abe
commit f6e0e9dc87
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 104 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
openlane/gpio_signal_buffering/config.tcl Normal file
View File

@ -0,0 +1,25 @@
# SPDX-FileCopyrightText: 2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set ::env(DESIGN_NAME) gpio_signal_buffering
set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_signal_buffering.v"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) "USE_POWER_PINS"

27
openlane/gpio_signal_buffering/interactive.tcl Normal file
View File

@ -0,0 +1,27 @@
# SPDX-FileCopyrightText: 2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
set script_dir [file dirname [file normalize [info script]]]
set save_path $script_dir/../..
# FOR LVS AND CREATING PORT LABELS
prep -design $script_dir -tag gpio_signal_buffering_lvs -overwrite
verilog_elaborate -log $::env(synthesis_logs)/synthesis.log
#init_floorplan
#file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
save_views -pnl_path $::env(CURRENT_NETLIST) -save_path $::env(CARAVEL_ROOT)
exit

25
openlane/gpio_signal_buffering_alt/config.tcl Normal file
View File

@ -0,0 +1,25 @@
# SPDX-FileCopyrightText: 2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set ::env(DESIGN_NAME) gpio_signal_buffering_alt
set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_signal_buffering_alt.v"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) "USE_POWER_PINS"

27
openlane/gpio_signal_buffering_alt/interactive.tcl Normal file
View File

@ -0,0 +1,27 @@
# SPDX-FileCopyrightText: 2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
set script_dir [file dirname [file normalize [info script]]]
set save_path $script_dir/../..
# FOR LVS AND CREATING PORT LABELS
prep -design $script_dir -tag gpio_signal_buffering_alt_lvs -overwrite
verilog_elaborate -log $::env(synthesis_logs)/synthesis.log
#init_floorplan
#file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
save_views -pnl_path $::env(CURRENT_NETLIST) -save_path $::env(CARAVEL_ROOT)
exit