update script to get the signoff sdc from directory `./signoff/<design name>/<design name>.sdc`

scripts/pt_sta.tcl

@@ -55,15 +55,17 @@ if {\
 
     # Reading constraints (signoff)
     if {$::env(DESIGN) == "mgmt_core_wrapper" | $::env(DESIGN) == "RAM256" | $::env(DESIGN) == "RAM128"} {
-      read_sdc $::env(MCW_ROOT)/sdc/$::env(DESIGN).sdc
+      read_sdc $::env(MCW_ROOT)/signoff/$::env(DESIGN)/$::env(DESIGN).sdc
     } else {
-      read_sdc $::env(CARAVEL_ROOT)/sdc/$::env(DESIGN).sdc
+      read_sdc $::env(CARAVEL_ROOT)/signoff/$::env(DESIGN)/$::env(DESIGN).sdc
     }
 
     # Reading parasitics based on the RC corner specified
     proc read_spefs {design rc_corner} {
       if {$design == "caravel"} {
+        set spef_mapping(flash_clkrst_buffers)                     $::env(CARAVEL_ROOT)/signoff/buff_flash_clkrst/openlane-signoff/buff_flash_clkrst.${rc_corner}.spef
         set spef_mapping(mprj)                                     $::env(UPRJ_ROOT)/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.${rc_corner}.spef
+       
         # add your module name instantiated in user_project_wrapper here
         # set spef_mapping(mprj/<instance name>)                     $::env(UPRJ_ROOT)/signoff/<design name>/openlane-signoff/spef/<design name>.${rc_corner}.spef
 

sdc/buff_flash_clkrst.sdc

@@ -1,79 +0,0 @@
-###############################################################################
-# Created by write_sdc
-# Thu Oct 13 17:28:51 2022
-###############################################################################
-current_design buff_flash_clkrst
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name __VIRTUAL_CLK__ -period 8.0000 
-set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[0]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[10]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[11]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[1]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[2]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[3]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[4]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[5]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[6]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[7]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[8]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[9]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[0]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[1]}]
-set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[2]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[0]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[1]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[2]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[0]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[10]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[11]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[1]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[2]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[3]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[4]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[5]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[6]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[7]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[8]}]
-set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[9]}]
-###############################################################################
-# Environment
-###############################################################################
-set_load -pin_load 0.0334 [get_ports {out_n[2]}]
-set_load -pin_load 0.0334 [get_ports {out_n[1]}]
-set_load -pin_load 0.0334 [get_ports {out_n[0]}]
-set_load -pin_load 0.0334 [get_ports {out_s[11]}]
-set_load -pin_load 0.0334 [get_ports {out_s[10]}]
-set_load -pin_load 0.0334 [get_ports {out_s[9]}]
-set_load -pin_load 0.0334 [get_ports {out_s[8]}]
-set_load -pin_load 0.0334 [get_ports {out_s[7]}]
-set_load -pin_load 0.0334 [get_ports {out_s[6]}]
-set_load -pin_load 0.0334 [get_ports {out_s[5]}]
-set_load -pin_load 0.0334 [get_ports {out_s[4]}]
-set_load -pin_load 0.0334 [get_ports {out_s[3]}]
-set_load -pin_load 0.0334 [get_ports {out_s[2]}]
-set_load -pin_load 0.0334 [get_ports {out_s[1]}]
-set_load -pin_load 0.0334 [get_ports {out_s[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[0]}]
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_fanout 10.0000 [current_design]