From f5a9d4677ea6ef8fd4038f93fbfcfa67b8fa4a34 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 5 Oct 2022 20:46:03 -0400
Subject: [PATCH] Revert "Implemented fix from early issue #16.  Finally
 decided to pull the"

This reverts commit 577cc12fe08a55c6f06fca8890c56383c124cc7f.

Reverting the change from issue #16.  After some discussion, it has
been decided that it is up to the user to implement the pull-up and
pull-down modes correctly by setting the output enable and driving
the output to the appropriate value.  Note that this should be well
documented, if by nothing else than a validation testbench that
excercises a user pull-up and pull-down input mode.
---
 manifest                         |  2 +-
 verilog/rtl/gpio_control_block.v | 25 ++++++-------------------
 2 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/manifest b/manifest
index fa4ee29f..e3c469fb 100644
--- a/manifest
+++ b/manifest
@@ -13,7 +13,7 @@ d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76  verilog/rtl/chip_io.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
 36af0303a0e84ce4a40a854ef1481f8a56bc9989  verilog/rtl/digital_pll.v
 ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-72c1bce09886b89608403aa517ddd74010627211  verilog/rtl/gpio_control_block.v
+1f894f1c43d42017c157d8dd7d2e4674c1a43303  verilog/rtl/gpio_control_block.v
 9c92ddf1391fa75ee906e452e168ca2cdd23bd18  verilog/rtl/gpio_defaults_block.v
 32d395d5936632f3c92a0de4867d6dd7cd4af1bb  verilog/rtl/gpio_logic_high.v
 b890e19f294294ee4aad4136b95c46e17d6f91dd  verilog/rtl/housekeeping.v
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index e4361b33..b77f081f 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -45,18 +45,7 @@
  * the clock half cycle.  This avoids the need to fine-tune the clock
  * skew between GPIO blocks.
  *
- * Modified 10/4/2022 by Tim Edwards
- * Replaces the tri-state output with a zero-value output when the
- * user project is powered down (same modification as was made to the
- * management protect module).  This allows all outputs to be buffered
- * and sized by the synthesis tools.
- *
- * Modified 10/5/2022 by Tim Edwards
- * Changed the behavior of the logic for the pad "out" and "oeb"
- * pins for the user so that they match the logic used for the
- * management SoC, which is to automatically control these values
- * when the configuration is set to either input pull-up or input
- * pull-down modes.
+ * Modified 10/05/2022 by Tim Edwards
  *
  *---------------------------------------------------------------------
  */
@@ -246,18 +235,16 @@ module gpio_control_block #(
     /* the control block.  In this case, the output enable state is	*/
     /* determined by the OEB configuration bit.				*/
 
-    assign pad_gpio_outenb =
-		(gpio_dm[2:1] == 2'b01) ? 1'b0 :
-		((mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ? gpio_outenb : 1'b0) :
-		user_gpio_oeb);
+    assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
+			gpio_outenb : 1'b0) : user_gpio_oeb;
 
     /* For 2-wire interfaces, if the pad is configured for pull-up or	*/
     /* pull-down, drive the output value locally to achieve the		*/
     /* expected pull.							*/
 
-    assign pad_gpio_out =
-		(gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] :
-		((mgmt_ena) ? mgmt_gpio_out : user_gpio_out);
+    assign pad_gpio_out = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
+			((gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] : mgmt_gpio_out) :
+			mgmt_gpio_out) : user_gpio_out; 
 
     /* Buffer user_gpio_in with an enable that is set by the user domain vccd */