From f499b8b75f44878aeba82cc7b35956dc6574e4c7 Mon Sep 17 00:00:00 2001 From: Passant Date: Fri, 14 Oct 2022 13:11:42 -0700 Subject: [PATCH] update top-level rtl with 7 pass through signals to be buffered inside the SoC --- verilog/rtl/caravel.v | 44 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index c7d9b037..8be8aba5 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -229,6 +229,16 @@ module caravel ( wire caravel_rstn_buf; wire clock_core_buf; + // SoC pass through buffered signals + wire mprj_io_loader_clock_buf; + wire mprj_io_loader_strobe_buf; + wire mprj_io_loader_resetn_buf; + wire mprj_io_loader_data_2_buf; + wire rstb_l_buf; + wire por_l_buf; + wire porb_h_buf; + + // top-level buffers buff_flash_clkrst flash_clkrst_buffers ( .in_n({ caravel_clk, @@ -312,8 +322,8 @@ module caravel ( .flash_io0(flash_io0), .flash_io1(flash_io1), // SoC Core Interface - .porb_h(porb_h), - .por(por_l), + .porb_h(porb_h_buf), + .por(por_l_buf), .resetb_core_h(rstb_h), .clock_core(clock_core), .gpio_out_core(gpio_out_core), @@ -409,7 +419,7 @@ module caravel ( wire mprj2_vdd_pwrgood; `ifdef USE_SRAM_RO_INTERFACE - // SRAM read-only access from houskeeping + // SRAM read-only access from housekeeping wire hkspi_sram_clk; wire hkspi_sram_csb; wire [7:0] hkspi_sram_addr; @@ -429,6 +439,22 @@ module caravel ( .VGND(vssd_core), `endif + // SoC pass through buffered signals + .serial_clock_in(mprj_io_loader_clock), + .serial_clock_out(mprj_io_loader_clock_buf), + .serial_load_in(mprj_io_loader_strobe), + .serial_load_out(mprj_io_loader_strobe_buf), + .serial_resetn_in(mprj_io_loader_resetn), + .serial_resetn_out(mprj_io_loader_resetn_buf), + .serial_data_2_in(mprj_io_loader_data_2), + .serial_data_2_out(mprj_io_loader_data_2_buf), + .rstb_l_in(rstb_l), + .rstb_l_out(rstb_l_buf), + .porb_h_in(porb_h), + .porb_h_out(porb_h_buf), + .por_l_in(por_l), + .por_l_out(por_l_buf), + // Clock and reset .core_clk(caravel_clk_buf), .core_rstn(caravel_rstn_buf), @@ -637,7 +663,7 @@ module caravel ( mprj_io_loader_data_1}; // Note that serial_link_2 is backwards compared to serial_link_1, so it // shifts in the other direction. - assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2, + assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf, gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]}; // Propagating clock and reset to mitigate timing and fanout issues @@ -656,15 +682,15 @@ module caravel ( assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0], mprj_io_loader_clock}; - assign gpio_clock_2_shifted = {mprj_io_loader_clock, + assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf, gpio_clock_2[`MPRJ_IO_PADS_2-1:1]}; assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0], mprj_io_loader_resetn}; - assign gpio_resetn_2_shifted = {mprj_io_loader_resetn, + assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf, gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]}; assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0], mprj_io_loader_strobe}; - assign gpio_load_2_shifted = {mprj_io_loader_strobe, + assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf, gpio_load_2[`MPRJ_IO_PADS_2-1:1]}; wire [2:0] spi_pll_sel; @@ -683,7 +709,7 @@ module caravel ( .ext_clk(clock_core_buf), .pll_clk(pll_clk), .pll_clk90(pll_clk90), - .resetb(rstb_l), + .resetb(rstb_l_buf), .sel(spi_pll_sel), .sel2(spi_pll90_sel), .ext_reset(ext_reset), // From housekeeping SPI @@ -699,7 +725,7 @@ module caravel ( .VPWR(vccd_core), .VGND(vssd_core), `endif - .resetb(rstb_l), + .resetb(rstb_l_buf), .enable(spi_pll_ena), .osc(clock_core_buf), .clockp({pll_clk, pll_clk90}),