From 0848d6b8f5f56cffb75005b8958b21534d025355 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 13 Sep 2023 06:20:15 -0700 Subject: [PATCH 1/2] Remove includes and add define macro to make it possible for new project to add logic --- verilog/rtl/toplevel_cocotb.v | 33 ++++++--------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/verilog/rtl/toplevel_cocotb.v b/verilog/rtl/toplevel_cocotb.v index e3e86060..a56754c5 100644 --- a/verilog/rtl/toplevel_cocotb.v +++ b/verilog/rtl/toplevel_cocotb.v @@ -1,31 +1,6 @@ `timescale 1 ns / 1 ps `include "includes.v" // in case of RTL coverage is needed and it doesn't work correctly without include files by this way -`ifdef VCS -`ifdef sky130 -`ifndef ENABLE_SDF - `include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v" - `include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v" - `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v" - `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" - `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" - `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" -`else - `include "cvc-pdk/sky130_ef_io.v" - `include "cvc-pdk/sky130_fd_io.v" - `include "cvc-pdk/primitives_hd.v" - `include "cvc-pdk/sky130_fd_sc_hd.v" - `include "cvc-pdk/primitives_hvl.v" - `include "cvc-pdk/sky130_fd_sc_hvl.v" -`endif // ~ ENABLE_SDF -`elsif gf180 // sky180 - `include "libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v" - // `include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/GF018hv5v_mcu_sc7_udp.v" - `include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/primitives.v" - `include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0.v" - // `include "libs.ref/gf180mcu_sc7_hv/verilog/GF018hv5v_mcu_sc7.v" - `include "libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v" -`endif //sky180 -`endif //VCS + module caravel_top ; @@ -39,10 +14,12 @@ initial begin `else $vcdplusfile("waves.vpd"); `endif + // $vcdplusmemorydump(); $vcdpluson(); `else $dumpfile ({"waves.vcd"}); $dumpvars (0, caravel_top); + `endif end `endif // WAVE_GEN @@ -216,7 +193,9 @@ caravel uut ( `endif // ! openframe - +`ifdef USE_USER_VIP + `USER_VIP +`endif // USE_USER_VIP // make speical variables for the mprj input to assign the input without writing to the output gpios // cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element From 312dbaea9096bb16a6e1e84c5fd464591584b3b9 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 13 Sep 2023 13:31:26 +0000 Subject: [PATCH 2/2] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index d8669400..82ce2289 100644 --- a/manifest +++ b/manifest @@ -52,7 +52,7 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 739ca5ed63a513d2e4c9bf3ecfad32d9fa527518 verilog/rtl/simple_por.v b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v -036dc8e9066082b2e133dc7b72fd3ad5a52f254b verilog/rtl/toplevel_cocotb.v +9178c87e3d5196fd3e6abae6fc310e1b663ade0e verilog/rtl/toplevel_cocotb.v 8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v 256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py 98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py