From e945c3b8825bec3e517634fbfc095808bf1f313d Mon Sep 17 00:00:00 2001
From: M0stafaRady <mostafa.rady@efabless.com>
Date: Mon, 3 Oct 2022 05:45:55 -0700
Subject: [PATCH] fix bug at mgmt_gpio_out by increasing the number of phases

---
 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py
index 9f513e67..83ba1478 100644
--- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py
+++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py
@@ -19,7 +19,7 @@ async def mgmt_gpio_out(dut):
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
     cocotb.log.info(f"[TEST] Start mgmt_gpio_out test")  
-    phases_fails = 2
+    phases_fails = 3
     phases_passes = 0 
     reg1 =0 # buffer
     reg2 = 0 #buffer
@@ -50,6 +50,7 @@ async def mgmt_gpio_out(dut):
                     await ClockCycles(caravelEnv.clk,10) 
             cocotb.log.info("[TEST] passing sending {reg1} blinks ")
             phases_fails -=1
+            phases_passes +=1
         await ClockCycles(caravelEnv.clk,10) 
 
     if phases_fails != 0: