From 8e02ea79d8e5c1413b51f83b59a9091248567982 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Tue, 22 Mar 2022 17:02:36 +0200 Subject: [PATCH 1/2] fix wrong cell name `sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1` --- verilog/rtl/gpio_control_block.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index bb50b83a..6bc3fab5 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -162,7 +162,7 @@ module gpio_control_block #( /* add a final logic gate after that. The logic gate is */ /* synthesized and will be sized appropriately for an output buffer */ - sky130_fd_sc_hd__dlygate4sd2 data_delay_1 ( + sky130_fd_sc_hd__dlygate4sd2_1 data_delay_1 ( `ifdef USE_POWER_PINS .VPWR(vccd), .VGND(vssd), @@ -173,7 +173,7 @@ module gpio_control_block #( .A(serial_data_pre), ); - sky130_fd_sc_hd__dlygate4sd2 data_delay_2 ( + sky130_fd_sc_hd__dlygate4sd2_1 data_delay_2 ( `ifdef USE_POWER_PINS .VPWR(vccd), .VGND(vssd), From 374deaec62bbb9f9ecd569c0829967cdad21aba4 Mon Sep 17 00:00:00 2001 From: kareefardi Date: Tue, 22 Mar 2022 15:03:30 +0000 Subject: [PATCH 2/2] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 4667a258..5bf04c90 100644 --- a/manifest +++ b/manifest @@ -13,7 +13,7 @@ d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v -3a62ce6627741ec3eaf798a23807ef15c46475a4 verilog/rtl/gpio_control_block.v +e4740845a6a543b5dcc74f5c356d5542d2e15f31 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v 5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v