From e81416bb511fc500b9706e61797b50cbfa5a9471 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 08:56:46 -0700 Subject: [PATCH] add new test mgmt_gpio_bidir --- verilog/dv/cocotb/tests.json | 6 ++ .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 62 ++++++++++++++++++- .../cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c | 61 ++++++++++++++++++ 3 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 3af944fb..7a8022b1 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -145,6 +145,12 @@ "GL":["nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], "description":"tests blinking of mgmt gpio bit as an output"} + ,"mgmt_gpio_bidir" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "} ,"timer0_oneshot" :{"level":0, "SW":true, "RTL":["setup","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 83ba1478..8ddcc7bd 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -1,4 +1,5 @@ import random +import re import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log @@ -103,4 +104,63 @@ async def mgmt_gpio_in(dut): if phases_fails != 0: cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") else: - cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + + + + +@cocotb.test() +@repot_test +async def mgmt_gpio_bidir(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=243058) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start mgmt_gpio_in test") + phases_fails = 3 + phases_passes = 0 + pass_list = (0x1B,0x2B,0xFF) + fail_list = tuple([0xEE]) + reg2 = 0 #buffer + + await wait_reg1(cpu,caravelEnv,0XAA) + num_blinks = random.randint(1, 20) + cocotb.log.info (f"[TEST] start send {num_blinks} blinks") + for i in range(num_blinks): + if i == num_blinks-1: #last iteration + # await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xFF) + cpu.write_debug_reg1_backdoor(0xFF) + caravelEnv.drive_mgmt_gpio(1) + await ClockCycles(caravelEnv.clk,4000) + caravelEnv.drive_mgmt_gpio(0) + await ClockCycles(caravelEnv.clk,4000) + cocotb.log.info(f"[TEST] finish sending {num_blinks} blinks ") + + cocotb.log.info(f"[TEST] waiting for {num_blinks} blinks ") + recieved_blinks = 0 + while True: + cocotb.log.info(f"[TEST] here 0 ") + if cpu.read_debug_reg2() == 0xFF: #test finish + break + while (True): + if caravelEnv.monitor_mgmt_gpio() == 0: + break + if cpu.read_debug_reg2() == 0xFF: #test finish + break + cocotb.log.info(f"[TEST] here 1 ") + await ClockCycles(caravelEnv.clk,10) + while (True): + if caravelEnv.monitor_mgmt_gpio() == 1: + recieved_blinks +=1 + break + if cpu.read_debug_reg2() == 0xFF: #test finish + break + cocotb.log.info(f"[TEST] here 2 ") + await ClockCycles(caravelEnv.clk,10) + await ClockCycles(caravelEnv.clk,1) + + + if recieved_blinks == num_blinks: + cocotb.log.info(f"[TEST] recieved the correct number of blinks {num_blinks}") + else: + cocotb.log.error(f"[TEST] recieved the incorrect number of blinks recieved = {recieved_blinks} expected = {num_blinks}") diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c new file mode 100644 index 00000000..001a5625 --- /dev/null +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +// -------------------------------------------------------- + +/* + * Management SoC GPIO Pin Test + * Tests writing to the GPIO pin. + */ + +void main() +{ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_gpio_mode1 = 1; + reg_gpio_mode0 = 0; // for full swing + + reg_gpio_ien = 1; + reg_gpio_oe = 0; + int num_blinks = 0; + reg_debug_1 = 0xAA; // start of the test + int z = reg_debug_1; + while (true) { + // reg_debug_2 = z; + // z= reg_debug_1; + while(reg_gpio_in == 0); + while(reg_gpio_in == 1); + num_blinks++; + if (reg_debug_1 == 0xFF) + break; + } + reg_gpio_ien = 0; + reg_gpio_oe = 1; + for (int i = 0; i < num_blinks; i++) { + /* Fast blink for simulation */ + reg_gpio_out = 1; + reg_gpio_out = 0; + } + reg_debug_2 = 0xFF; //finish test + + +} +