Merge pull request #440 from efabless/tapeout_updates

Tapeout updates

Makefile

@@ -122,9 +122,8 @@ __ship:
 		drc off; \
 		crashbackups stop; \
 		addpath hexdigits; \
-		addpath $(CARAVEL_ROOT)/mag; \
-		addpath $(UPRJ_ROOT)/mag; \
 		addpath $(MCW_ROOT)/mag; \
+		addpath $(UPRJ_ROOT)/mag; \
 		load user_project_wrapper; \
 		property LEFview true; \
 		property GDS_FILE $(UPRJ_ROOT)/gds/user_project_wrapper.gds; \
@@ -132,7 +131,8 @@ __ship:
 		load $(UPRJ_ROOT)/mag/user_id_programming; \
 		load $(UPRJ_ROOT)/mag/user_id_textblock; \
 		load $(CARAVEL_ROOT)/maglef/simple_por; \
-		load $(UPRJ_ROOT)/mag/caravel -dereference; \
+		load $(UPRJ_ROOT)/mag/caravel_core -dereference; \
+		load caravel -dereference; \
 		select top cell; \
 		expand; \
 		cif *hier write disable; \
@@ -1144,7 +1144,7 @@ __set_user_id:
 	# sed -r "s/^(\s*project_id\s*:\s*).*/\1${USER_ID}/" -i info.yaml
 	cp $(CARAVEL_ROOT)/mag/user_id_programming.mag ./mag/user_id_programming.mag
 	cp $(CARAVEL_ROOT)/mag/user_id_textblock.mag ./mag/user_id_textblock.mag
-	cp $(CARAVEL_ROOT)/verilog/rtl/caravel.v ./verilog/rtl/caravel.v
+	cp $(CARAVEL_ROOT)/verilog/rtl/caravel_core.v ./verilog/rtl/caravel_core.v
 	cp $(CARAVEL_ROOT)/verilog/gl/user_id_programming.v ./verilog/gl/user_id_programming.v
 	python3 $(CARAVEL_ROOT)/scripts/set_user_id.py $(USER_ID) $(shell pwd) 2>&1 | tee ./signoff/build/set_user_id.out
 

manifest

@@ -45,6 +45,6 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524  verilog/rtl/mprj_io_buffer.v
 6f802b6ab7e6502160adfe41e313958b86d2c277  verilog/rtl/simple_por.v
 b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v
-c94f7ed5aa311f005513ace344991c8e6d3d19f5  scripts/set_user_id.py
+256190717faa72005cf7656d8443c4c0693b3f78  scripts/set_user_id.py
 98168b1fb6f80b196f9a05e725ec6ad99bc57ac6  scripts/generate_fill.py
 3210e724c6dc99563af780ff1778fada5b432604  scripts/compositor.py

scripts/set_user_id.py

@@ -180,7 +180,7 @@ if __name__ == '__main__':
             idrex = re.compile("parameter USER_PROJECT_ID = 32'h([0-9A-F]+);")
 
             # Check if USER_PROJECT_ID has a non-zero value in caravel.v
-            rtl_top_path = user_project_path + '/verilog/rtl/caravel.v'
+            rtl_top_path = user_project_path + '/verilog/rtl/caravel_core.v'
             if os.path.isfile(rtl_top_path):
                 with open(rtl_top_path, 'r') as ifile:
                     vlines = ifile.read().splitlines()
@@ -307,7 +307,7 @@ if __name__ == '__main__':
     print('Step 2:  Add user project ID parameter to source verilog.')
 
     changed = False
-    with open(vpath + '/rtl/caravel.v', 'r') as ifile:
+    with open(vpath + '/rtl/caravel_core.v', 'r') as ifile:
         vlines = ifile.read().splitlines()
         outlines = []
         for line in vlines:
@@ -319,12 +319,12 @@ if __name__ == '__main__':
             outlines.append(oline)
 
     if changed:
-        with open(vpath + '/rtl/caravel.v', 'w') as ofile:
+        with open(vpath + '/rtl/caravel_core.v', 'w') as ofile:
             for line in outlines:
                 print(line, file=ofile)
             print('Done!')
     else:
-        print('Error:  No substitutions done on verilog/rtl/caravel.v.')
+        print('Error:  No substitutions done on verilog/rtl/caravel_core.v.')
         print('Ending process.')
         sys.exit(1)