diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index 5b357042..3751c4ee 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -1375,7 +1375,6 @@ module caravan (
 		.X(rstb_l)
     );
 
-    `ifdef USE_SPARE_LOGIC
     // Spare logic for metal mask fixes
     wire [107:0] spare_xz_nc;
     wire [15:0] spare_xi_nc;
@@ -1400,8 +1399,6 @@ module caravan (
 		.spare_xfq(spare_xfq_nc),
 		.spare_xfqn(spare_xfqn_nc)
     );
-    `endif
-
 
 endmodule
 // `default_nettype wire
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3a8e082e..315fbc30 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1427,7 +1427,6 @@ module caravel (
 		.X(rstb_l)
     );
 
-    `ifdef USE_SPARE_LOGIC
     // Spare logic for metal mask fixes
     wire [107:0] spare_xz_nc;
     wire [15:0] spare_xi_nc;
@@ -1452,7 +1451,6 @@ module caravel (
 		.spare_xfq(spare_xfq_nc),
 		.spare_xfqn(spare_xfqn_nc)
     );
-    `endif
 
 endmodule
 // `default_nettype wire