Merge pull request #355 from efabless/cleanup

Cleanup & documentation

docs/rst/ECO.rst

@@ -0,0 +1,37 @@
+.. raw:: html
+
+   <!---
+   # SPDX-FileCopyrightText: 2020 Efabless Corporation
+   #
+   # Licensed under the Apache License, Version 2.0 (the "License");
+   # you may not use this file except in compliance with the License.
+   # You may obtain a copy of the License at
+   #
+   #      http://www.apache.org/licenses/LICENSE-2.0
+   #
+   # Unless required by applicable law or agreed to in writing, software
+   # distributed under the License is distributed on an "AS IS" BASIS,
+   # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   # See the License for the specific language governing permissions and
+   # limitations under the License.
+   #
+   # SPDX-License-Identifier: Apache-2.0
+   -->
+
+====================
+CARAVEL TOPLEVEL ECO
+====================
+
+ECOs were done on top level caravel for several reasons
+
+1. `porb_h_in` shorted with `por_l_in` because it was a floating wire
+2. `mgmt_gpio_oeb` was not shorted with `mprj_io_one` in some instances of `gpio_control_block`, this is due to an issue with the router
+3. To get caravel device level LVS clean, mask layer in the IO cells in the library needed modifications, can be found in `gds/caravel+io.gds`
+
+The non-eco'd views coming out of OpenLane is postfixed by `-openlane`, for example: `gds/caravel-openlane.gds.gz`
+
+After applying `scripts/create_top_pins.sh` on `caravel.mag`, the views have a postfix `-with-labels`
+
+The eco'd views have postfix `-eco`
+
+After running tapeout scripts on `caravel.mag`, the views have a postfix `-signoff`

signoff/caravel_clocking/final_summary_report.csv

@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h1m28s0ms,0h1m19s0ms,93000.0,0.006,46500.0,73.79,689.33,279,0,0,0,0,0,0,0,0,0,0,-1,6041,2106,0.0,0.0,-1,-0.11,-1,0.0,0.0,-1,-0.37,-1,3401586.0,0.0,36.83,19.27,0.36,0.0,0.0,212,262,67,117,0,0,0,210,0,3,4,17,12,16,12,41,79,86,5,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.74,0,sky130_fd_sc_hd,0,4

signoff/digital_pll/final_summary_report.csv

@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/ma/ef/caravel_openframe/openlane/digital_pll,digital_pll,digital_pll,flow completed,0h0m56s0ms,0h0m47s0ms,110933.33333333334,0.005625,55466.66666666667,81.42,551.6,312,0,0,0,0,0,0,0,0,0,0,-1,5632,2218,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3849516.0,0.0,32.42,24.29,0.0,0.0,0.0,613,808,120,303,0,0,0,646,4,3,17,11,331,19,12,27,31,72,20,46,50,0,96,90.9090909090909,11.0,10.0,AREA 0,6,50,1,40,40,0.82,0,sky130_fd_sc_hd,0,4

signoff/gpio_control_block/final_summary_report.csv

@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/marwan/work/caravel_user_project/caravel/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow completed,0h1m34s0ms,0h1m22s0ms,-2.0,0.01105,-1,69.84,500.38,-1,0,0,0,0,0,0,0,0,0,-1,-1,4224,991,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,4147542.0,0.0,11.38,14.38,15.24,-1,13.41,57,85,50,78,0,0,0,42,2,13,13,0,13,0,0,4,29,44,4,38,28,0,66,20.0,50.0,50,DELAY 0,5,50,1,25,16.9,0.7,0.05,sky130_fd_sc_hd,0,4

signoff/housekeeping/final_summary_report.csv

@@ -1,2 +0,0 @@
-design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/openlane/designs/housekeeping,housekeeping,CARAVEL_3,flow completed,0h27m39s0ms,0h9m48s0ms,-2.0,0.20397821850000003,-1,27.46,1920.61,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,537830,74553,0.0,-0.06,0.0,0.0,0.0,0.0,-0.06,0.0,0.0,0.0,335718259.0,0.0,59.79,79.59,27.73,54.13,10.77,8363,9422,189,1195,0,0,0,9086,156,1,144,323,4521,44,5,170,942,889,20,388,2646,0,3034,189331.584,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,AREA 0,20,50,1,153.6,153.18,0.28,0.3,sky130_fd_sc_hd,3

signoff/mgmt_protect/final_summary_report.csv

@@ -1,2 +0,0 @@
-design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/openlane/designs/mgmt_protect,mgmt_protect,RUN_3,flow completed,0h7m19s0ms,0h1m55s0ms,-2.0,0.304,-1,3.25,1261.57,-1,0,0,0,0,0,0,9,-1,-1,-1,-1,783964,29113,-1.28,-2.11,0.0,0.0,0.0,-42.18,-104.65,0.0,0.0,0.0,747220322.0,0.0,67.42,17.31,45.23,3.7,-1,176,2014,48,1886,0,0,0,921,333,0,0,0,0,0,0,0,1088,626,2,194,4006,0,4200,277421.0688,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,8.0,125.0,8,AREA 0,10,50,1,472.190,36.720,0.11,0.05,sky130_fd_sc_hd,4