From de2f4a37071668b52944192f9fbf4bff82fe8985 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 08:38:00 -0700 Subject: [PATCH] Add bitbang_spi_i test --- verilog/dv/cocotb/tests.json | 7 ++ .../dv/cocotb/tests/bitbang/bitbang_spi_i.c | 64 +++++++++++++++++++ .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 56 +++++++++++++++- 3 files changed, 125 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index f2cd2ee0..30c81df6 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -71,6 +71,13 @@ "SW":true, "description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"} + ,"bitbang_spi_i" :{"level":0, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "SW":true, + "description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"} + ,"hk_regs_wr_wb" :{"level":0, "SW":false, "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c new file mode 100644 index 00000000..4c310438 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c @@ -0,0 +1,64 @@ +#include +#include + +// Empty C code + +void main() +{ + int i,j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = 0x1803; + reg_mprj_io_36 = 0x1803; + reg_mprj_io_35 = 0x1803; + reg_mprj_io_34 = 0x1803; + reg_mprj_io_33 = 0x1803; + reg_mprj_io_32 = 0x1803; + reg_mprj_io_31 = 0x1803; + reg_mprj_io_30 = 0x1803; + reg_mprj_io_29 = 0x1803; + reg_mprj_io_28 = 0x1803; + reg_mprj_io_27 = 0x1803; + reg_mprj_io_26 = 0x1803; + reg_mprj_io_25 = 0x1803; + reg_mprj_io_24 = 0x1803; + reg_mprj_io_23 = 0x1803; + reg_mprj_io_22 = 0x1803; + reg_mprj_io_21 = 0x1803; + reg_mprj_io_20 = 0x1803; + reg_mprj_io_19 = 0x1803; + reg_mprj_io_18 = 0x1803; + reg_mprj_io_17 = 0x1803; + reg_mprj_io_16 = 0x1803; + reg_mprj_io_15 = 0x1803; + reg_mprj_io_14 = 0x1803; + reg_mprj_io_13 = 0x1803; + reg_mprj_io_12 = 0x1803; + reg_mprj_io_11 = 0x1803; + reg_mprj_io_10 = 0x1803; + reg_mprj_io_9 = 0x1803; + reg_mprj_io_8 = 0x1803; + reg_mprj_io_7 = 0x1803; + reg_mprj_io_6 = 0x1803; + reg_mprj_io_5 = 0x1803; + reg_mprj_io_4 = 0x1803; + reg_mprj_io_3 = 0x1803; + reg_mprj_io_2 = 0x1803; + reg_mprj_io_1 = 0x1803; + reg_mprj_io_0 = 0x1803; + + reg_debug_1 = 0xFF; // finish configuration + + reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + while (reg_mprj_datal != 0x8F66FD7B); + reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal + while (reg_mprj_datal != 0xFFA88C5A); + reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal + while (reg_mprj_datal != 0xC9536346); + + reg_debug_2 = 0xFF; + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 4c910271..6d864ffc 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -200,7 +200,7 @@ async def bitbang_cpu_all_i(dut): -"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI.""" +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as output.""" @cocotb.test() @repot_test async def bitbang_spi_o(dut): @@ -262,4 +262,56 @@ async def bitbang_spi_o(dut): i |= 0x80000000 - await ClockCycles(caravelEnv.clk, 10) \ No newline at end of file + await ClockCycles(caravelEnv.clk, 10) + + +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as input.""" +@cocotb.test() +@repot_test +async def bitbang_spi_i(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=56703) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured + #Configure all as output except reg_mprj_io_3 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 18 and 19 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 17 and 20 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 16 and 21 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 15 and 22 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 14 and 23 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 13 and 24 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 12 and 25 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 11 and 26 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 10 and 27 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 9 and 28 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 8 and 29 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 7 and 30 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 6 and 31 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 5 and 32 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 4 and 33 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 3 and 34 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 2 and 35 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37 + await load_spi(caravelEnv) # load + + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info("[TEST] finish configuring using bitbang") + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xBB) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xFFA88C5A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xCC) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xC9536346 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + + await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") \ No newline at end of file