diff --git a/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/mag/xres_buf.mag similarity index 100% rename from mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag rename to mag/xres_buf.mag diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index ab5e5047..ead1d1bf 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -1338,7 +1338,7 @@ module caravan ( ); // XRES (chip input pin reset) reset level converter - sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ( + xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), diff --git a/verilog/rtl/caravan_netlists.v b/verilog/rtl/caravan_netlists.v index ef061b87..61aa6b25 100644 --- a/verilog/rtl/caravan_netlists.v +++ b/verilog/rtl/caravan_netlists.v @@ -64,7 +64,7 @@ `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_logic_high.v" - `include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" + `include "gl/xres_buf.v" `include "gl/caravan.v" `else `include "digital_pll.v" @@ -82,7 +82,7 @@ `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" - `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" + `include "xres_buf.v" `include "mgmt_core_wrapper.v" `include "caravan.v" `endif diff --git a/verilog/rtl/caravan_openframe.v b/verilog/rtl/caravan_openframe.v index 4512d638..5131789b 100644 --- a/verilog/rtl/caravan_openframe.v +++ b/verilog/rtl/caravan_openframe.v @@ -1216,7 +1216,7 @@ module caravan_openframe ( ); // XRES (chip input pin reset) reset level converter - sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ( + xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index c10772f4..cffb17e1 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -1391,7 +1391,7 @@ module caravel ( ); // XRES (chip input pin reset) reset level converter - sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ( + xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index bc1c1618..14916d47 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -60,7 +60,7 @@ `include "gl/gpio_control_block.v" `include "gl/gpio_defaults_block.v" `include "gl/gpio_logic_high.v" - `include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" + `include "gl/xres_buf.v" `include "gl/caravel.v" `else `include "digital_pll.v" @@ -78,7 +78,7 @@ `include "gpio_control_block.v" `include "gpio_defaults_block.v" `include "gpio_logic_high.v" - `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" + `include "xres_buf.v" `include "mgmt_core_wrapper.v" `include "caravel.v" `endif diff --git a/verilog/rtl/caravel_openframe.v b/verilog/rtl/caravel_openframe.v index 8e57925b..b619a7ec 100644 --- a/verilog/rtl/caravel_openframe.v +++ b/verilog/rtl/caravel_openframe.v @@ -1275,7 +1275,7 @@ module caravel_openframe ( ); // XRES (chip input pin reset) reset level converter - sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ( + xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), diff --git a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v b/verilog/rtl/xres_buf.v similarity index 80% rename from verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v rename to verilog/rtl/xres_buf.v index 19f19b08..333d8227 100644 --- a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v +++ b/verilog/rtl/xres_buf.v @@ -13,7 +13,12 @@ // limitations under the License. // SPDX-License-Identifier: Apache-2.0 -module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ( +// Module xres_buf is a level-shift buffer between the xres pad (used for +// digital reset) and the caravel chip core. The xres pad output is in +// the 3.3V domain while the signal goes to the digital circuitry in the +// 1.8V domain. + +module xres_buf ( X , A , `ifdef USE_POWER_PINS