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caravel
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update caravel.py to disable bin 3 also

This commit is contained in:
M0stafaRady 2022-10-08 01:56:41 -07:00
parent 2dc29bb207
commit d90001eac2
2 changed files with 3 additions and 9 deletions
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2
verilog/dv/cocotb/caravel.py
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@ -58,8 +58,6 @@ class Caravel_env:
async def disable_bins(self):
for i in range(38):
if i == 3:
continue
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins"""

10
verilog/dv/cocotb/tests/irq/IRQ_external.py
View File

@ -8,13 +8,9 @@ from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from caravel import GPIO_MODE
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
async def write_reg_spi(caravelEnv,address,data):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@ -62,7 +58,7 @@ async def IRQ_external(dut):
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when mprj 7 deasserted")
elif reg1 in fail_list: # pass phase
if reg1 == 0x1E:
cocotb.log.info(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted")
cocotb.log.error(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted")
elif reg1 == 0x2E:
cocotb.log.error(f"[TEST] Failed interrupt is detected when mprj 7 deasserted")
else: