diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 0c1d6ed5..6d3509e3 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -605,12 +605,12 @@ module caravel (
     // Clocking control
 
     caravel_clocking clocking(
-        `ifdef USE_POWER_PINS
-            .vdd1v8(VPWR),
-            .vss(VGND),
-        `endif
+    `ifdef USE_POWER_PINS
+		.VPWR(VPWR),
+		.VGND(VGND),
+    `endif
         .ext_clk_sel(ext_clk_sel),
-        .ext_clk(clock),
+        .ext_clk(clock_core),
         .pll_clk(pll_clk),
         .pll_clk90(pll_clk90),
         .resetb(resetb),
@@ -631,7 +631,7 @@ module caravel (
         `endif
         .resetb(resetb),
         .enable(spi_pll_ena),
-        .osc(clock),
+        .osc(clock_core),
         .clockp({pll_clk, pll_clk90}),
         .div(spi_pll_div),
         .dco(spi_pll_dco_ena),
@@ -641,13 +641,13 @@ module caravel (
     // Housekeeping interface
 
     housekeeping housekeeping (
-        `ifdef USE_POWER_PINS
-            .vdd(VPWR),
-            .vss(VGND),
-        `endif
+    `ifdef USE_POWER_PINS
+		.VPWR(VPWR),
+		.VGND(VGND),
+    `endif
 
         .wb_clk_i(caravel_clk),
-        .wb_rst_i(~caravel_rstn),
+        .wb_rstn_i(caravel_rstn),
 
         .wb_adr_i(mprj_adr_o_core),
         .wb_dat_i(mprj_dat_o_core),
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index cc0af252..3f62e810 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -18,8 +18,8 @@
 
 module caravel_clocking(
 `ifdef USE_POWER_PINS
-    input vdd1v8,
-    input vss,
+    input VPWR,
+    input VGND,
 `endif
     input resetb, 	// Master (negative sense) reset
     input ext_clk_sel,	// 0=use PLL clock, 1=use external (pad) clock
diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v
index 6f43ee4f..4589238b 100644
--- a/verilog/rtl/housekeeping.v
+++ b/verilog/rtl/housekeeping.v
@@ -61,13 +61,13 @@ module housekeeping #(
     parameter IO_CTRL_BITS = 13
 ) (
 `ifdef USE_POWER_PINS
-    inout vdd,
-    inout vss, 
+    inout VPWR,
+    inout VGND, 
 `endif
 
     // Wishbone interface to management SoC
     input wb_clk_i,
-    input wb_rst_i,
+    input wb_rstn_i,
     input [31:0] wb_adr_i,
     input [31:0] wb_dat_i,
     input [3:0] wb_sel_i,
@@ -260,6 +260,10 @@ module housekeeping #(
 
     assign reset = (pass_thru_mgmt_reset) ? 1'b1 : reset_reg;
 
+	// Invert wb_rstn_i
+	wire wb_rst_i;
+	assign wb_rst_i = ~wb_rstn_i;
+	
     // Handle the management-side control of the GPIO pins.  All but the
     // first and last three GPIOs (0, 1 and 35 to 37) are one-pin interfaces with
     // a single I/O pin whose direction is determined by the local OEB signal.