diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index d6c1ab90..7923f332 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -379,6 +379,7 @@ module caravan (
     wire [31:0] hk_dat_i;
     wire hk_ack_i;
     wire hk_stb_o;
+    wire hk_cyc_o;
 
     // Exported Wishbone Bus (user area facing)
     wire 	mprj_cyc_o_user;
@@ -457,6 +458,7 @@ module caravan (
 	.mprj_dat_i(mprj_dat_i_core),
 
 	.hk_stb_o(hk_stb_o),
+	.hk_cyc_o(hk_cyc_o),
 	.hk_dat_i(hk_dat_i),
 	.hk_ack_i(hk_ack_i),
 
@@ -713,7 +715,7 @@ module caravan (
 	.wb_dat_i(mprj_dat_o_core),
 	.wb_sel_i(mprj_sel_o_core),
 	.wb_we_i(mprj_we_o_core),
-	.wb_cyc_i(mprj_cyc_o_core),
+	.wb_cyc_i(hk_cyc_o),
 	.wb_stb_i(hk_stb_o),
 	.wb_ack_o(hk_ack_i),
 	.wb_dat_o(hk_dat_i),