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revert clock to be assigned to anything so iverilog will not remove it

This commit is contained in:
M0stafaRady 2023-10-30 09:03:18 -07:00
parent dbde8a5696
commit ca4a54f5f1
1 changed files with 10 additions and 0 deletions
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10
verilog/rtl/toplevel_cocotb.v
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@ -153,6 +153,8 @@ caravel uut (
);
`endif // CPU_TYPE_ARM
`else // ! openframe
wire dummy_wire_clk; // iverilog ignores clock_tb if it's not assigned
assign dummy_wire_clk = clock_tb;
caravel_openframe uut (
.vddio (vddio_tb),
.vssio (vssio_tb),
@ -171,6 +173,14 @@ caravel uut (
.gpio (mprj_io_tb),
.resetb (resetb_tb)
);
assign gpio_tb = 0;
assign vddio_2_tb = 0;
assign vssio_2_tb = 0;
assign vdda1_2_tb = 0;
assign vssa1_2_tb = 0;
`endif // ! openframe
`ifdef USE_USER_VIP