From 298ede362bba8ff7232f7af3ffc500c6155d2f2c Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 7 Jun 2022 10:42:56 -0400 Subject: [PATCH 1/2] Corrects an issue with the user pass-through flash programming mode in which the data and clock are activated simultaneously, so the first data bit after CSB goes low may or may not be seen by the SPI flash. --- verilog/rtl/housekeeping.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v index bb4e20f4..76a5807e 100644 --- a/verilog/rtl/housekeeping.v +++ b/verilog/rtl/housekeeping.v @@ -803,7 +803,7 @@ module housekeeping #( assign mgmt_gpio_out_pre[31:16] = mgmt_gpio_data[31:16]; assign mgmt_gpio_out_pre[12:11] = mgmt_gpio_data[12:11]; - assign mgmt_gpio_out_pre[10] = (pass_thru_user) ? mgmt_gpio_in[2] + assign mgmt_gpio_out_pre[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2] : mgmt_gpio_data[10]; assign mgmt_gpio_out_pre[9] = (pass_thru_user) ? mgmt_gpio_in[4] : mgmt_gpio_data[9]; From 485d9df7e3b343e536a1d1bf22679e40d7224259 Mon Sep 17 00:00:00 2001 From: RTimothyEdwards Date: Tue, 7 Jun 2022 14:46:03 +0000 Subject: [PATCH 2/2] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index af5987a9..6768382d 100644 --- a/manifest +++ b/manifest @@ -16,7 +16,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 41f899d8a8510f933e08e41d1b4ac13d84191f38 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v -5469b880904d6dd5d1eba6f026b3582810df412c verilog/rtl/housekeeping.v +cf97aef32db28c44e3750e201867d5bf9243e151 verilog/rtl/housekeeping.v 3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v 0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v