From c5d251bc08c735a33e9a01e33e52b931068ee2c8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 17 May 2023 00:23:41 -0700 Subject: [PATCH] fix some syntax error in caravan --- verilog/rtl/caravan.v | 12 ++++++------ verilog/rtl/caravan_core.v | 6 ++++-- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index 318ce852..cbcbda33 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -396,13 +396,13 @@ module caravan ( .mprj_io_analog_sel(mprj_io_analog_sel), .mprj_io_analog_pol(mprj_io_analog_pol), .mprj_io_dm(mprj_io_dm), - .mprj_gpio_analog(user_gpio_analog), - .mprj_gpio_noesd(user_gpio_noesd), - .mprj_analog(user_analog), - .mprj_clamp_high(user_clamp_high), - .mprj_clamp_low(user_clamp_low) + .user_gpio_analog(user_gpio_analog), + .user_gpio_noesd(user_gpio_noesd), + .user_analog(user_analog), + .user_clamp_high(user_clamp_high), + .user_clamp_low(user_clamp_low), // Loopbacks to constant value 1 in the 1.8V domain - .mprj_io_one(mprj_io_one), + .mprj_io_one(mprj_io_one) ); copyright_block copyright_block(); diff --git a/verilog/rtl/caravan_core.v b/verilog/rtl/caravan_core.v index 667bf160..8e2e70c1 100644 --- a/verilog/rtl/caravan_core.v +++ b/verilog/rtl/caravan_core.v @@ -281,7 +281,9 @@ module caravan_core ( wire caravel_rstn; - assign mgmt_io_in_hk = mgmt_io_in; + assign mgmt_io_in_hk[13:0] = mgmt_io_in[13:0]; + assign mgmt_io_in_hk[24:14] = {mprj_io_zero[5],mprj_io_zero[4], mprj_io_zero[4],mprj_io_zero[3], mprj_io_zero[3],mprj_io_zero[2], mprj_io_zero[2],mprj_io_zero[1], mprj_io_zero[1],mprj_io_zero[0], mprj_io_zero[0]}; + assign mgmt_io_in_hk[37:25] = mgmt_io_in[37:25]; assign mgmt_io_out = mgmt_io_out_hk; assign mgmt_io_oeb = mgmt_io_oeb_hk; @@ -1379,6 +1381,6 @@ module caravan_core ( (* keep *) empty_macro empty_macro_0 (); (* keep *) empty_macro empty_macro_1 (); (* keep *) caravan_power_routing caravan_power_routing(); -(* keep *) caravan_signal_routing caravan_signal_routing(); +// (* keep *) caravan_signal_routing caravan_signal_routing(); endmodule // `default_nettype wire \ No newline at end of file