Merge pull request #409 from efabless/makefile_fix

Makefile fix

.github/workflows/auto-update.yml

@@ -36,7 +36,7 @@ jobs:
       - name: Set up Python
         uses: actions/setup-python@v2
         with:
-          python-version: 3.6
+          python-version: 3.8
       - name: Install dependencies
         run: python -m pip install --upgrade pip
       - name: Run creating README.rst

Makefile

@@ -46,6 +46,8 @@ MCW_ROOT?=$(PWD)/mgmt_core_wrapper
 MCW ?=LITEX_VEXRISCV
 MPW_TAG ?= mpw-8c
 
+PYTHON_BIN ?= python3
+
 # PDK switch varient
 export PDK?=sky130A
 
@@ -1227,15 +1229,19 @@ endif
 
 .PHONY: pdk-with-volare
 pdk-with-volare: check-python install-volare 
-	@volare enable ${OPEN_PDKS_COMMIT}
+	./venv/bin/volare enable ${OPEN_PDKS_COMMIT}
 
 check-python:
 ifeq ($(shell which python3),)
 $(error Please install python 3.6+)
 endif
 
+.PHONY: install-volare
 install-volare:
-	python3 -m pip install --upgrade volare
+	rm -rf ./venv
+	$(PYTHON_BIN) -m venv ./venv
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir volare
 
 
 ###########################################################################

manifest

@@ -23,14 +23,14 @@ f2242e1f295ee5efeacea51698f706a2cfd97c28  verilog/rtl/chip_io_alt.v
 653b230c7cbf092a6210ba7820bc942f312e53f3  verilog/rtl/debug_regs.v
 2a7b5d508735fd485f8adcb3f8766ea3830091c2  verilog/rtl/digital_pll.v
 ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8  verilog/rtl/gpio_control_block.v
-9c92ddf1391fa75ee906e452e168ca2cdd23bd18  verilog/rtl/gpio_defaults_block.v
+5465dde450a43c14a6902887d189088dbdc5bfe3  verilog/rtl/gpio_control_block.v
+6aae2132de98430b8195c4f32a9da6329b86b024  verilog/rtl/gpio_defaults_block.v
 32d395d5936632f3c92a0de4867d6dd7cd4af1bb  verilog/rtl/gpio_logic_high.v
 406b6eba38e0a7e8ff561dc4e5395dbefc9c175c  verilog/rtl/gpio_signal_buffering.v
 45ea4a2d466d6d70e9e86011a62c1bd3f706ef99  verilog/rtl/gpio_signal_buffering_alt.v
-f468ac85865e146c29368acec881382096eb417c  verilog/rtl/housekeeping.v
+7ba9d7552eb3bbe4c7c11e2b8464be3c09d91e0b  verilog/rtl/housekeeping.v
 34c6ab585986a00216c72f2f1fea0e5a8523867b  verilog/rtl/housekeeping_spi.v
-ee3fbd794fcc6d221562147b09891e315873ac4c  verilog/rtl/mgmt_protect.v
+0a00fd77505b29c1367b2c21d0bbc940fc50ab01  verilog/rtl/mgmt_protect.v
 3b1ff20593bc386d13f5e2cf1571f08121889957  verilog/rtl/mgmt_protect_hv.v
 9816acedf3dc3edd193861cc217ec46180ac1cdd  verilog/rtl/mprj2_logic_high.v
 c96ba94e5779ea6afe452d89632eaada73e26aab  verilog/rtl/mprj_io.v
@@ -39,7 +39,7 @@ c96ba94e5779ea6afe452d89632eaada73e26aab  verilog/rtl/mprj_io.v
 4edbfd0ad80b69a799a399ffc717b560fcae615b  verilog/rtl/pads.v
 669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
 6f802b6ab7e6502160adfe41e313958b86d2c277  verilog/rtl/simple_por.v
-1b1705d41992b318c791a5703e0d43d0bcda8f12  verilog/rtl/spare_logic_block.v
+b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v
 c94f7ed5aa311f005513ace344991c8e6d3d19f5  scripts/set_user_id.py
 98168b1fb6f80b196f9a05e725ec6ad99bc57ac6  scripts/generate_fill.py